Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-22
2005-11-22
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06968532
ABSTRACT:
A mask pattern may be decomposed into two or more masks, each having a pitch greater than that of the original mask pattern. New, “partial-pattern” masks may be created for each of the new mask patterns. The original mask pattern is transferred to the photoresist for the corresponding layer using a multiple exposure technique in which the photoresist is exposed with each of the partial-pattern masks individually, e.g., back-to-back in a pass through a scanner, to define all of the features in the original pattern.
REFERENCES:
patent: 6444483 (2002-09-01), Minemura et al.
patent: 6553562 (2003-04-01), Capodieci et al.
patent: 6635392 (2003-10-01), Okada et al.
patent: 6738859 (2004-05-01), Liebchen
patent: 2002/0166107 (2002-11-01), Capodieci et al.
patent: 2004/0003368 (2004-01-01), Hsu et al.
patent: 2004/0010770 (2004-01-01), Broeke et al.
Frost Rex K.
Nguyen Phi
Sivakumar Swaminathan (Sam)
Fish & Richardson P.C.
Intel Corporation
Siek Vuthe
Tat Binh
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