Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1996-06-03
1998-10-27
Loring, Susan A.
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438592, 438626, 438631, H01L 21469, H01L 21302, H01L 21465
Patent
active
058277820
ABSTRACT:
A method for forming a Spin-On-Glass (SOG) residue free Inter-Metal Dielectric (IMD) spacer layer as a substrate layer for a void free conformal insulator layer within a high aspect ratio exceedingly narrowly spaced patterned layer within an integrated circuit. First there is provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a first aperture formed therein. Formed upon the patterned layer and into the first aperture is a conformal Inter-Metal Dielectric (IMD) layer. The conformal Inter-Metal Dielectric (IMD) layer has a second aperture formed therein where the conformal Inter-Metal Dielectric (IMD) layer is formed into the first aperture. Formed upon the conformal Inter-Metal Dielectric (IMD) layer and filling the second aperture is a planarizing Spin-On-Glass (SOG) layer. There is then etched selectively and isotropically through a selective and isotropic etch the planarizing Spin-On-Glass (SOG) layer to leave remaining a Spin-On-Glass (SOG) layer residue within the second aperture. Finally, there is then etched non-selectively and anisotropically through a non-selective and anisotropic etch the Spin-On-Glass (SOG) layer residue and the conformal Inter-Metal Dielectric (IMD) layer to leave remaining an Inter-Metal Dielectric (IMD) spacer layer adjoining the patterned layer.
REFERENCES:
patent: 5382547 (1995-01-01), Sultan et al.
patent: 5639345 (1997-06-01), Huang et al.
patent: 5665657 (1997-09-01), Lee
Ackerman Stephen B.
Loring Susan A.
Saile George O.
Szecsy Alek P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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