Multiple etch contact etching method incorporating post...

Details Multiple etch contact etching method incorporating post... Multiple etch contact etching method incorporating post...

2000-04-24

2002-04-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S637000, C438S638000, C438S706000, C438S727000, C438S724000, C438S738000, C438S743000, C438S744000, C438S963000

Reexamination Certificate

active

06376384

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming vias through dielectric layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming residue free vias through dielectric layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication device densities have increased and microelectronic fabrication device dimensions have decreased, it has become increasingly important within advanced microelectronic fabrications to form through dielectric layers within those advanced microelectronic fabrications vias, such as but not limited to contact vias and interconnection vias, of similarly commensurately decreased cross-sectional dimensions such that the vias may be formed through the dielectric layers within the advanced microelectronic fabrications without compromising the enhanced levels of integration desired within the advanced microelectronic fabrications.
A representative but by no means limiting integrated circuit microelectronic fabrication structure which illustrates one of several problems encountered when forming through a dielectric layer within an advanced integrated circuit microelectronic fabrication a contact via within the advanced integrated circuit microelectronic fabrication is illustrated by the schematic cross-sectional diagram of FIG.
1
.
Shown in
FIG. 1
is a semiconductor substrate
10
having formed therein an active region of the semiconductor substrate
10
defined by a pair of isolation regions
12
a
and
12
b.
Within and upon the active region of the semiconductor substrate
10
is formed an adjoining pair of field effect transistors (FETs) which share a source/drain region
20
b
formed within the active region of the semiconductor substrate
10
. Employed in forming the adjoining pair of field effect transistors (FETs) is a pair of gate electrode stacks comprising: (1) a pair of gate dielectric layers
14
a
and
14
b
having formed and aligned thereupon; (2) a pair of gate electrode layers
16
a
and
16
b
which in turn have formed and aligned thereupon; (3) a pair of gate electrode dielectric cap layers
18
a
and
18
b.
In addition, there is formed within the semiconductor substrate
10
adjoining the pair of gate electrode stacks a series of source/drain regions
20
a,
20
b
and
20
c
which are partially obscured by a series of dielectric spacer layers
22
a,
22
b,
22
c
and
22
d
formed adjoining the edges of the pair of gate electrode stacks. Finally, there is shown within
FIG. 1
a blanket planarized premetal metal dielectric (PMD) layer
24
formed over the semiconductor substrate
10
including the adjoining pair of field effect transistors (FETs), where the blanket planarized pre-metal dielectric (PMD) layer
24
has formed thereupon a pair of patterned photoresist layers
26
a
and
26
b.
As is understood by a person skilled in the art, when the gate electrode stacks within
FIG. 1
are formed with a first separation width W
1
upon the active region of the semiconductor substrate
10
and the first separation width W
1
approximates a minimum resolvable separation width achievable with an advanced photoexposure apparatus, a second separation width W
2
of the pair of dielectric spacer layers
22
b
and
22
c
which is typically formed adjoining the pair of gate electrode stacks while employing a self aligned reactive ion etch (RIE) anisotropic etching method will of necessity be less than the minimum resolvable separation width achievable with the advanced photoexposure apparatus. Similarly, presuming that the same photoexposure apparatus is employed in forming the patterned photoresist layers
26
a
and
26
b
as is employed in defining the separation width W
1
of the gate electrode stacks, the patterned photoresist layers
26
a
and
26
b
will also have a minimum separation width W
1
which approximates the minimum separation width achievable with the advanced photoexposure apparatus. The patterned photoresist layers
26
a
and
26
b
will also have a registration tolerance variation (not shown in FIG.
1
) which typically displaces the patterned photoresist layers
26
a
and
26
b
with respect to the gate electrode stacks.
In order to avoid forming an oversized and misaligned contact via through the portion of the blanket planarized pre-metal dielectric (PMD) layer
24
between the dielectric spacer layers
22
b
and
22
c
when accessing the source/drain region
20
b
within the active region of the semiconductor substrate
10
, it is known in the art to employ a selective reactive ion etch (RIE) method which forms, in part, the contact via through the blanket planarized pre-metal dielectric (PMD) layer
24
in a self aligned fashion. The results of forming the contact via through such a selective reactive ion etch (RIE) method are illustrated in FIG.
2
.
Shown in
FIG. 2
is a schematic cross-sectional diagram of an integrated circuit microelectronic fabrication otherwise equivalent to the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in
FIG. 1
, but wherein the contact via
27
has been etched while employing the selective reactive ion etch (RIE) method to expose the portion of the source/drain region
20
b
not obscured by the dielectric spacer layers
22
b
and
22
c.
As illustrated within
FIG. 2
, the selective reactive ion etch (RIE) method etches the dielectric material from which is formed the blanket planarized pre-metal dielectric (PMD) layer
24
but does not appreciably etch the dielectric material from which is formed the dielectric spacer layers
22
b
and
22
c.
Within typical integrated circuit microelectronic fabrications analogous or equivalent to the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG.
1
and
FIG. 2
, it is common in the art of integrated circuit fabrication to employ pre-metal dielectric (PMD) layers, such as the blanket planarized pre-metal dielectric (PMD) layer
24
, formed from a silicon oxide dielectric material, while simultaneously employing dielectric spacer layers, such as the dielectric spacer layers
22
b
and
22
c,
formed from a silicon nitride dielectric material. When employing within an integrated circuit whose schematic cross-sectional diagram is analogous or equivalent to the integrated circuit whose schematic cross-sectional diagram is illustrated in
FIG. 1
a pre-metal dielectric (PMD) layer formed of a silicon oxide dielectric material and a dielectric spacer layer formed of a silicon nitride material, it is possible to employ a selective reactive ion etch (RIE) method which typically employs a novel etchant gas composition comprising a fluorocarbon etchant gas to form with a substantial etch selectivity of the pre-metal dielectric (PMD) layer with respect to the dielectric spacer layer within the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG.
2
.
While the use of a selective reactive ion etch (RIE) method employing a novel etchant gas composition comprising a perfluorocarbon etchant gas may readily provide from the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in
FIG. 1
the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in
FIG. 2
without compromising the width of the contact via
27
accessing the source/drain region
20
b,
under such circumstances the integrated circuit microelectronic fabrication whose schematic cross-sectional diagram is illustrated in
FIG. 2
is typically not formed without problems. In particular, there is typically formed, as illustrated in
FIG. 2
, a fluorocarbon polymer residue layer
28

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