Multiple equilibration circuits for a single bit line

Details Multiple equilibration circuits for a single bit line Multiple equilibration circuits for a single bit line

1998-06-03

2000-03-07

Phan, Trong

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438228, 438936, H01L 218238

Patent

active

060339454

ABSTRACT:
According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

REFERENCES:
patent: 4578128 (1986-03-01), Mundt et al.
patent: 5843813 (1998-12-01), Wei et al.
patent: 5950079 (1999-09-01), Honeycutt et al.

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