Multiple deposition of metal layers for the fabrication of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S396000, C438S240000, C438S647000, C438S685000

Reexamination Certificate

active

06916704

ABSTRACT:
An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

REFERENCES:
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patent: 5905279 (1999-05-01), Nitayama et al.
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 6100200 (2000-08-01), Van Buskirk et al.
patent: 6674113 (2004-01-01), Goldbach et al.
Yamada, K. et al.: “A Deep-Trenched Capacitor Technology For 4 Mega Bit Dynamic Ram”, IEEE, 1985, 29.3, pp. 702-705.
Ishiuchi, H. et al.: “Submicron CMOS Technologies For Four Mega Bit Dynamic Ram”, IEEE, 1985, 29.4, pp. 706-709.

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