Multiple BIST controllers for testing multiple embedded memory a

Details Multiple BIST controllers for testing multiple embedded memory a Multiple BIST controllers for testing multiple embedded memory a

1997-12-29

1999-11-30

Teska, Kevin J

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714718, G06F 1127

Patent

active

059957310

ABSTRACT:
Multiple memory arrays (215, 225) in embedded applications are each tightly coupled to their own Built-In Self-Test (BIST) controller to form BISTed memory cells (210, 220) supporting structural and retention testing. Testing on multiple BISTed memories (210, 220) is initiated by common INVOKE (230), RETENTION (240), and RELEASE (250) signals. DONE and HOLD signals are combined (260, 280) from the multiple BISTed memories (210, 220) and delayed to generate a global "all memory" DONE (265) and HOLD (285) signals. FAIL signals are combined (270) from the multiple BISTed memories (210, 220) to generate a global "any memory" FAIL (275) signal. The BISTed memories can be combined in multiple stages to meet power limitations.

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Luige Ternullo, Jr., et al., `Deterministic Self-Test of a High-Speed embedded Memory and Logic Processor Subsystem`, 1995 IEEE International Test Conference, pp. 33-44.
Ian Burgess, et al., `Practical design techniques for memory BIST`, Electronic Design, vol. 45, p. 106, May 12, 1997,

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