Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
2001-08-14
2004-10-26
Lee, Thomas (Department: 2115)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S005000, C710S040000, C712S011000, C712S015000, C712S016000
Reexamination Certificate
active
06810434
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates broadly to signal processing and, more particularly, to interfacing with a variety of multimedia signals.
BACKGROUND OF THE INVENTION
Field programmable logic and in particular, field programmable gate arrays (FPGAs), have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, such reconfigurable arrays have been used to enhance customer product flexibility in ways that no other technology can currently match.
Microprocessors have traditionally been used to satisfy time to market and end product flexibility needs. This solution may not meet performance constraints and lacks the concurrency possible in an unconstrained hardware design. Typical design processes, therefore, reach a point where the overall design is partitioned into hardware and software components. An interface is defined and the design process continues along two parallel paths. Sometime later, the software and hardware components must be integrated. Problems usually develop at this point because of interface misinterpretation or partitioning that cannot meet design requirements. This impacts the hardware, the software and the schedule. If the hardware design is realized in programmable logic, the hardware can be manipulated as easily as the software.
Products which adapt to the end user's particular requirements, through self-directed or end user directed reconfiguration, are becoming more prevalent. As the number of modes of operation increases, mode-specific hardware becomes a less cost-effective solution. In the case where the end user is truly directing the adaptation, predetermined hardware solutions become unacceptable. Reconfigurable logic enables design solutions where dynamic hardware/software re-partitioning is possible.
Programmable logic not only vastly improves the time necessary to implement a static design, but significant time to market and product feature benefits can be realized when hardware can dynamically be altered as easily as software.
To reduce design cycles, designers have also turned towards high level design languages (e.g., HDL) and logic synthesis tools. Many programmable logic solutions are poorly suited to this design methodology, however. An incompatibility exists between logic synthesis algorithms originally developed for gate-level design and the block-like structures found on many programmable logic devices. This can result in significant under utilization or degraded performance. In either case a more expensive device is required. Real gate-level programmable devices are ideally suited to this design methodology.
When schematic-based design methods are used, some programmable logic solutions impose significant constraints on design implementation to ensure satisfactory results. This imposition tends to bind the design to a particular programmable device and requires a significant learning investment. Any design specification changes which impact design decisions made to fit this imposed structure can have disastrous effects on utilization and performance and can potentially require a more expensive device or even a costly redesign. Gate-level programmable devices, coupled with sophisticated, timing-driven, implementation tools, minimize device-specific optimization.
Any design process includes a significant amount of learning. Usually engineers spend most of this time learning about product requirements or prototyping critical portions of the design to prove implementation feasibility. Many programmable logic solutions are not “push button”. Time must be spent learning programmable device architecture or implementation tool quirks. Worse yet, the design may require modification or manual component placement to meet design targets. This increases the cost and time to market.
The discipline of multimedia signal processing typifies the challenges discussed hereinabove. Various emerging and evolving multimedia standards continue to create substantial confusion in the design of appropriate IC (and systems incorporating ICs) architecture(s). The current “solutions” to these problems can broadly be characterized as:
dedicated multiple chipsets, along with some number of interface chips; and
programmable engines, specific to a particular standard, along with some number of interface chips.
Each of these “solutions” requires multiple chips, and either a very expensive custom system/board combination of chips for each application or an inefficient use of multiple chips to meet a specific application. Hence, there is a need for a solution to facilitate multimedia system or subsystem design using a single IC chip which is adaptable (or readily configurable) to a variety of standards.
Discussion of the Prior Art
The following documents, all of which are US patents, all of which are incorporated by reference herein, disclose various techniques having some relevance to the present invention.
U.S. Pat. No. 5,696,959 (December 1997) discloses memory store from a selected one of a register pair conditional upon the state of a selected status bit.
U.S. Pat. No. 5,696,954 (December 1997) discloses three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically ANDed with a third input logically ORed with the sum/difference logically ANDed with an inverse of the third input.
U.S. Pat. No. 5,680,339 (October 1997) discloses method and rounding using redundant coded multiply result. See also U.S. Pat. No. 5,644,522 (July 1997) which discloses method, apparatus and system for multiply rounding using redundant coded multiply result.
U.S. Pat. No. 5,644,790 (July 1997) discloses a universal CD ROM interface using single interface connection.
U.S. Pat. No. 5,644,524 (July 1997) discloses an iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR.
U.S. Pat. No. 5,625,836 (April 1997) discloses SIMD/MIMD processing memory element (PME).
U.S. Pat. No. 5,606,677 (February 1997) discloses a packet word multiply operation forming output including most significant bits of product and other bits of one input.
U.S. Pat. No. 5,603,012 (February 1997) discloses a start code detector.
U.S. Pat. No. 5,600,847 (February 1997) discloses a three input arithmetic logic unit with mask generator. See also related U.S. Pat. No. 5,590,350 (December 1996).
U.S. Pat. No. 5,590,345 (December 1996) discloses an advanced parallel array processor (APAP). See also related U.S. Pat. No. 5,588,152 (December 1996) which discloses an advanced parallel processor including advanced support hardware.
U.S. Pat. No. 5,577,213 (November 1996) discloses a multi-level adaptor card for computer.
U.S. Pat. No. 5,522,082 (May 1996) discloses a graphics display processor, a graphics display system and method of processing graphics data with control signals connected to a central processing unit and graphics circuits.
U.S. Pat. No. 5,512,896 (April 1996) discloses a Huffman encoding method, circuit and system employing most significant bit change for size detection,
U.S. Pat. No. 5,511,211 (April 1996) discloses a method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions.
U.S. Pat. No. 5,504,920 (April 1996) discloses a video driver system for communicating specific primitive commands to multiple video controller types.
U.S. Pat. No. 5,479,166 (December 1995) discloses a Huffman encoding method, circuit and system employing conditional subtraction for conversion of negative numbers.
U.S. Pat. No. 5,404,555 (April 1995) discloses a macro instruction set computer architecture.
U.S. Pat. No. 5,379,388 (January 1995) discloses digital signal processing apparatus with sequencer designating program routines.
U.S. Pat. No. 4,744,054 (May 1988) discloses a semiconductor device with a memory circuit.
Glossary
Unless otherwise noted
Muthujumaraswathy Kumaraguru
Rostoker Michael D.
Cao Chun
Kawasaki Microelectronics Inc.
Lee Thomas
Linden Gerald E.
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