Multilevel poly-Si tiling for semiconductor circuit manufacture

Details Multilevel poly-Si tiling for semiconductor circuit manufacture Multilevel poly-Si tiling for semiconductor circuit manufacture

2006-12-12

2006-12-12

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S183000, C438S195000, C438S241000, C438S243000, C438S244000, C438S245000, C438S246000, C438S247000, C438S252000, C438S253000, C438S258000, C438S622000, C438S623000, C438S773000, C438S774000, C257SE21243, C257SE21244, C257SE21688, C257SE21689

Reexamination Certificate

active

07148103

ABSTRACT:
Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by:manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE);manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE;providing a tile structure (25; 26);providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); andexposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.

REFERENCES:
patent: 5361234 (1994-11-01), Iwasa
patent: 5441915 (1995-08-01), Lee
patent: 5607868 (1997-03-01), Chida et al.
patent: 6030876 (2000-02-01), Koike
patent: 6458655 (2002-10-01), Yuzuriha et al.
Wolf et al. Silicon Processing for the VLSI Era, vol. 1—Process Technology, Second Edition, Lattice Press 2000, pp. 666-667.

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