Multilevel interconnect structure containing air gaps and...

Details Multilevel interconnect structure containing air gaps and... Multilevel interconnect structure containing air gaps and...

2002-05-13

2004-05-18

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S618000, C257S758000, C257S750000, C257S759000

Reexamination Certificate

active

06737725

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to air gap-containing metal/insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated (ULSI) devices and packaging, and more particularly to structures, methods, and materials relating to the incorporation of air gaps into multiple levels of multilayer interconnect structures.
BACKGROUND OF THE INVENTION
Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips are typically effected by multilevel interconnect structures containing patterns of metal wiring layers called traces. Wiring structures within a given trace or level of wiring are separated by an intralevel dielectric, while the individual wiring levels are separated from each other by layers of an interlevel dielectric. Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces.
By means of their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed, and thus chip performance. Signal-propagation delays are due to RC time constants wherein ‘R’ is the resistance of the on-chip wiring, and ‘C’ is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material, and by using interlevel and intralevel dielectrics (ILDS) with lower dielectric constants, k.
A preferred metal/dielectric combination for low RC interconnect structures is copper metal with a dielectric such as SiO
2
(k~4.0). Due to difficulties in subtractively patterning copper, copper-containing interconnect structures are typically fabricated by a damascene process. In a typical damascene process, metal patterns, which are inset in a layer of dielectric, are formed by the steps of: (i) etching holes (for vias) or trenches (for wiring) into the interlevel or intralevel dielectric; (ii) optionally, lining the holes or trenches with one or more adhesion or diffusion barrier layers; (iii) overfilling the holes or trenches with a metal wiring material; and (iv) removing the metal overfill by a planarizing process such as chemical-mechanical polishing (CMP), leaving the metal even with the upper surface of the dielectric.
The above-mentioned processing steps can be repeated until the desired number of wiring and via levels have been fabricated.
Fabrication of interconnect structures by damascene processing can be substantially simplified by using a process variation known as dual damascene, in which patterned cavities for the wiring level and its underlying via level are filled in with metal in the same deposition step. Dual damascene reduces the number of metal polishing steps by a factor of two, providing substantial cost savings, but requires that a dual-relief pattern be introduced into the combined via+wiring level dielectric.
Low-k alternatives to SiO
2
include carbon-based solid materials such as diamond-like carbon (DLC), also known as amorphous hydrogenated carbon (a-C:H), fluorinated DLC (FDLC), SiCO or SiCOH compounds, and organic or inorganic polymer dielectrics. Nanoporous versions of SiO
2
and the above-mentioned carbon-based materials have even lower k values, while air gaps have the lowest k values of any material (k~1.00). (Note that the air in the air gap may comprise any gaseous material or vacuum.)
Examples of multilayer interconnect structures incorporating air gaps are described, for example, in U.S. Pat. No. 5,461,003 by Havemann, et al.; U.S. Pat. No. 5,869,880, by Grill, et al.; and U.S. Pat. No. 5,559,055 by Chang, et al.
One preferred prior art method for forming air gaps utilizes a sacrificial place-holder (SPH) material which is removed or extracted from beneath a solid, semi-permeable, or perforated bridge layer. Examples of SPH materials and removal methods include poly (methylmethacrylate) (PMMA), poly-para-xylylene (Parylene™), amorphous carbon, and polystyrene, which may be removed by organic solvents, oxygen ashing, and/or low temperature (~200° C.) oxidation, and norborene-based materials such as BF Goodrich's Unity Sacrificial Polymer™, which may be removed by low temperature (350°-400° C.) thermal decomposition into volatiles. In the case of the Unity™ material, the volatile decomposition by-product actually diffuses through the bridge layer, as demonstrated by Kohl et al., Electrochemical and Solid-State Letters 149 (1998) for structures comprising SiO
2
(500 nm) bridge layers deposited by a low temperature plasma enhanced chemical vapor deposition (PECVD) process.
Compared to structures with solid dielectrics, air gap-based structures have lower thermal conductivity, reduced mechanical strength, and higher permeability to moisture and oxygen. Workable schemes for incorporating air gaps into interconnect structures must take these limitations into account. A further concern with air gap dielectrics is that they leave metal wiring features more susceptible to the opens and shorts induced by electromigration-driven mass transport, since the wiring features are no longer dimensionally constrained by being embedded in a solid dielectric.
Another concern is that structures with air gaps may not be as uniformly planar as structures built with intrinsically more rigid solid dielectrics. This can be a problem if locally depressed areas are formed by bridge layer sag over unsupported air gaps, since metal filling these depressed areas will remain in the structure after chemical-mechanical polishing (CMP) and be a source of shorts and/or extra capacitance.
In view of the drawbacks mentioned hereinabove with prior art processes, there is a continued need for developing a new and improved method in which air gaps can be formed in an interconnect without exhibiting any of the above-mentioned problems.
SUMMARY OF THE INVENTION
It is thus a general object of the present invention to provide a multilayer interconnect structure containing air gaps.
It is a further object of the present invention to provide an air gap-containing interconnect structure which is resistant to electromigration failure and environmental corrosion.
Another object of the present invention is to provide an air gap-containing interconnect structure which maximizes air gap volume fraction (relative to total volume fraction of dielectric), while minimizing the amount of unsupported wiring.
A still further object of the present invention is to provide a cost-effective and scalable method for fabricating multilevel interconnect structures having air gaps.
An even further object of the present invention is to, provide a method for-forming air gap-containing interconnect structures which minimizes the amount of processing that air gaps in the structure will experience during the fabrication of the structure.
Another object of the present invention is to provide a method for forming air gap-containing interconnect structures which minimizes the number of extra processing steps associated with (i) extraction of the sacrificial place-holder (SPH) material; and (ii) forming and/or patterning and/or pinching-off bridge layers through which the SPH must be removed.
The present invention provides a multilevel air gap-containing interconnect structure, and a workable, straightforward method for its fabrication. A preferred embodiment of the inventive structure includes a combination of an “air gap plus solid” via-level dielectric (with the solid dielectric only under the lines) plus a mostly air gap line-level dielectric.
The fabrication method forms planar via plus line level pairs embedded in a dielectric matrix comprising predefined regions of a permanent dielectric and predefined regions of a sacrificial place-holder (SPH) material. A dielectric bridge layer containing holes or perforations is formed on the structure after the desired number of pair levels have been assembled. The SPH in all the levels is then selectively removed

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