Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-31
2002-07-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S619000
Reexamination Certificate
active
06423629
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for multilevel copper interconnects with low-k dielectric constants and air gaps.
BACKGROUND OF THE INVENTION
As the integrated circuit (IC) technology makes rapid progress toward 100 nm gate transistors, the speed limiting factor is no longer the transistor delay, but the RC delay associated with the metal interconnects. A great deal of work is being done in this area on new and innovative materials and fabrication techniques to reduce the capacitance and thus reduce RC delay of interconnects. Currently studied low-k dielectrics include fluorinated silicon dioxide (SiO
2
), aerogels, and polymers. Additionally, as IC technology continues to scale, the aspect ratio of metal lines increases and the intra-level line-to-line capacitance increasingly dominates over the inter-level capacitance. Thus, it becomes increasingly important to implement low-k schemes between tightly spaced metal lines and less so between metal levels.
One approach to reducing the RC delay is provided in copending and commonly assigned application; application Ser. No. 09/483881, entitled “Selective Electroless-Plated Copper Metallization,” which is hereby incorporated by reference. Further, an article by B. Shieh et al., entitled “Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance,”
IEEE Electron Devices Letters,
19, no. 1, p. 16-18 (1998) presented simulations and some initial experimental results showing the possible capacitance reduction achievable using air-gap structures.
Another approach is described in an article by T. Ueda et al., entitled “A Novel Air Gap Integration Scheme for Multi-level Interconnects using Self-aligned Via Plugs,” 1998 Symposium on VLSI Technology,
Digest of Technical Papers,
p. 46-47 (1998) in which an air-gap structure was introduced between lines and SiO
2
was provided between metal levels. As described in this article, an effective dielectric constant of 1.8 at 0.3 micrometer (&mgr;m) line spacing was obtained. The authors of this article used the combination of PE-CVD SiO
2
with poor step coverage characteristics to intentionally form the air gaps, and biased HDP-CVD SiO
2
with good filling capability for the formation of inter-metal dielectric (IMD). In another approach described by J. G. Fleming et al., entitled “Use of Air Gap Structures to Lower Intra-level Capacitance,”
Proceedings of
1997
Dielectrics for ULSI Multi-level Interconnect Conference,
p. 139 (1997) a process of fabricating air-gap structures to lower intra-level capacitance was introduced. The authors of this article used an oxide deposition process with poor step coverage to create the desired air gaps. Yet another approach is described in U.S. Pat. No. 5,900,668, by D. L. Wollesen, entitled “Low Capacitance Interconnection,” issued May 4, 1999, which describes a scheme in which the parasitic capacitance is reduced by removing sections of dielectric inter-layers by anisotropic etching to form air-gaps which can remain or be filled with another dielectric material with a lower dielectric constant. An example of a prior art multilevel metallization scheme according to this process is provided in FIG.
1
.
Still, all of these approaches either involve complex additional processing steps or fail to provide an added benefit of reducing both intral-level line to line capacitance and the inter-level capacitance. Accordingly, there remains a need in the art to provide streamlined, improved methods and structures for alleviating the capacitance problems associated with via and metal line fabrication processes as design rules shrink.
SUMMARY OF THE INVENTION
The above mentioned problems associated with integrated circuit size and performance, the via and metal line formation process, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are provided which include a selective electroless copper metallization. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance.
In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material.
In one embodiment, depositing a low dielectric constant material includes depositing an organic silica film. In one embodiment, depositing a low dielectric constant material between the number of metal lines and the substrate using a directional process includes using a microwave plasma-assisted supersonic jet deposition process. In another, depositing a low dielectric constant material between the number of metal lines and the substrate using a directional process includes using a quasi hydrogen-free chemical vapor deposition process. In another, depositing a low dielectric constant material includes forming a low dielectric constant film by radio frequency plasma enhanced chemical vapor deposition using tetramethylsilane. In still another, depositing a low dielectric constant material includes depositing a polymer-like organic thin film by plasma-enhance chemical vapor deposition using a para-xylene precursor.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5356672 (1994-10-01), Schmitt, III et al.
patent: 5792706 (1998-08-01), Michael et al.
patent: 5900668 (1999-05-01), Wollesen
patent: 6140456 (2000-10-01), Lee et al.
patent: 6159842 (2000-12-01), Chang et al.
patent: 6214719 (2001-04-01), Nag
patent: 6218282 (2001-04-01), Buynoski
Fleming, J.G., et al., “Use Of Air Gap Structures To Lower Level Intralevel Capacitance”,Proceedings of the 1997 Dielectrics for ULSI Multi-level Interconnect Conference, p. 140, (1997).
Grill, A., et al., “Low dielectric constant films prepared by plasma-enhanced chemical vapor deposition from tetramethvisilane”,Journal of Applied Physics, 85(6), pp. 3314-3318, (1999).
Hymes, S., et al., “Passivation of Copper by Silicide Formation in Dilute Silane”,Conference Proceedings ULSI-VII, pp. 425-431, (1992).
Quan, Y.C., et al., “Polymer-like Organic Thin Films Deposited by Plasma Enhanced Chemical Vapor Deposition Using the Para-xylene Precursor as Low Dielectric Constant Interlayer Dielectrics for Multilevel Metallization”,Jpn. J. Appl. Phys, 38, pp. 1356-1358, (1999).
Shieh, B., et al., “Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance”,IEEE Electron Device Letters, 19(1), pp. 16-18, (1998).
Uchida, Y., et al., “A Flourinated Organic-Silica Film with Extremely Low Dielectric Constant”,Jpn. J. Appl. Phys., 38, pp. 2368-2372, (Apr. 1999).
Ueda, T., et al., “A novel Air Gap Integration Scheme for Multi-level Interconnects using Self-aligned Via Plugs”,Symposium on VLSI Technology Digest of Technical Papers, pp. 46-47, (1998).
Ahn Kie Y.
Forbes Leonard
Dang Phuc T.
Nelms David
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