Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2000-07-13
2002-06-18
Lam, Cathy (Department: 1775)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S698000, C257S773000, C257S774000, C257S776000, C174S260000, C174S261000, C361S772000, C361S774000, C361S777000
Reexamination Certificate
active
06407460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayer circuit board, for mounting thereon a semiconductor chip and/or other electronic elements, having lattice-arranged connection terminals and to a semiconductor device including the multilayer circuit board having a semiconductor chip and/or other electronic elements mounted thereon.
2. Description of the Related Art
FIG. 8
shows a semiconductor device composed of a monolayer circuit board
5
provided with a semiconductor chip
4
mounted thereon by flip-chip bonding. The semiconductor chip
4
has a electrode terminal carrying surface
2
having a peripheral area in which electrode terminals
6
are arranged in one row or line and are electrically connected to one end of the lead wiring lines
7
lying on the circuit board
5
.
FIG. 9
shows a plane arrangement of the lead wiring lines
7
and connection terminal pads
8
arranged in two rows or lines on the circuit board
5
. The connection terminal pads
8
have the same plane arrangement as that of the electrode terminals
6
of the semiconductor chip
4
. The connection terminal pads
8
on the outermost line have the lead wiring lines
7
directly extending outward and the other connection terminals
8
have the lead wiring lines
7
outwardly extending through a space between neighboring connection terminal pads
8
on the outer most line.
FIG. 10
shows a semiconductor device composed of a multilayer circuit board
50
including four circuit boards
5
a
to
5
d
, and a semiconductor chip
4
mounted thereon and having many rows or lines of electrode terminals
6
. Lead wiring lines
7
are disposed on separate layers
5
a
to
5
d
to avoid interference therebetween. The four circuit boards
5
a
to
5
d
having respective lead wiring lines
7
formed thereon are laminated to provide electrical connection of all the electrode terminals
5
to external connection terminals
9
. The lead wiring lines
7
are composed of lateral portions
7
a
lying on the circuit boards
5
a
to
5
d
and via portions
7
b
penetrating through one or more of the circuit boards
5
a
to
5
d
, in which the vias
7
b
provide electrical connection from the electrode terminals
6
to the lateral portions
7
a
or from the lateral portions
7
a
to the external connection terminals
9
.
On the electrode terminal carrying surface
2
of the semiconductor chip
4
, the electrode terminals
6
are usually arranged in a grid form, a staggered form, a close-packed form or the like, which can be collectively referred to as a lattice arrangement. A circuit board for mounting a semiconductor chip
4
thereon has connection terminal pads
8
formed thereon in an arrangement corresponding to that of the electrode terminals
6
on the electrode terminal carrying surface
2
of the semiconductor chip
4
, in which the distance or space between neighboring connection terminal pads
8
is determined so that at least one of the lead wiring lines
7
can run through the space.
Upgrading of the semiconductor chip requires an increased number of input/output terminals or connection terminals and an increased number or density of the connection terminal pads
8
.
FIG. 11
shows actual pad arrangements, i.e., (a) a grid form, (b) a staggered form and (c) a close-packed form. The nearest neighboring pads
8
have a space s therebetween. The space s must be sufficiently large to allow at least one of the lead wiring lines
7
to run therethrough. On the other hand, the space s is desirably as small as possible to provide an increased density of the pads
8
for an increased number of input/output terminals of a semiconductor chip. The lower limit of the space s also depends on a process tolerance which can be stably achieved in the production process.
If the pads
8
are arranged with a space s as small as the process tolerance, none of the lead wiring lines
7
can run through the space s. Namely, although lead wiring lines
7
can directly extend from the pads
8
on the outermost line of the lattice, additional wiring layers are necessary to enable lead wiring lines
7
to extend from the pads
8
on the inner lines of the lattice to avoid interference between lead wiring lines. This undesirably increases the number of wiring layers, which should be reduced to achieve an improved production efficiency.
An increase in the number of the wiring layers also causes a problem in the product yield, the product reliability and the production cost. Although an increased number of wiring layers can be achieved by a build-up process or the like, the technological difficulty is increased with the increase in the number of wiring layers, which involves an additional problem of ensuring the interlayer electrical connection while ensuring an improved wiring density in the respective layers, including good electrical connection over the entire wiring as a whole.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are grid- or stagger-arranged in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability.
Another object of the present invention is to provide a semiconductor device using the improved multilayer circuit board.
To achieve the object according to the present invention, there is provided a multilayer circuit board comprising:
a base board having a mounting surface for mounting thereon a semiconductor chip and/or other electronic elements having lattice-arranged connection terminals;
connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads;
lead wiring lines lying on the mounting surface and having one end connected to the connection terminal pads and the other end extending outward from the plane lattice; and
the said plane lattice having a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads.
According to a preferred embodiment, the vacant lattice areas have an open outer side and a closed inner side defined by the connection terminal pads in a number of r defined by:
r=b
(
d+s
)/(
w+s
),
d>s
and
d>w,
where b is a number of vacant lattice sites occupied by no connection terminal pads on the open outer side, d is a diameter of the pads, w is a width of the lead wiring lines and s is a distance between neighboring pads and is also a distance between neighboring lead wiring lines, said r connection terminal pads each having a lead wiring line having one end connected thereto and the other end extending outward from the plane lattice.
Typically, the vacant lattice areas are in the form of a triangle or a trapezoid having a base defined by an outermost line of the vacant lattice sites.
The present invention also provides a semiconductor device comprising the above-specified multilayer circuit board having a semiconductor chip and/or other electronic elements mounted thereon by area-array bonding.
REFERENCES:
patent: 5444303 (1995-08-01), Greenwood et al.
patent: 5677575 (1997-10-01), Maeta et al.
patent: 5784262 (1998-07-01), Sherman
patent: 6008543 (1999-12-01), Iwabuchi
patent: 6107685 (2000-08-01), Nishiyama
patent: 6194668 (2001-02-01), Horiuchi et al.
patent: 6215184 (2001-04-01), Stearns et al.
patent: 6242815 (2001-06-01), Hsu et al.
patent: 898 311 (1999-01-01), None
patent: A-11-186332 (1999-07-01), None
Horiuchi Michio
Mizuno Shigeru
Lam Cathy
Pennie & Edmonds LLP
Shinko Electric Industries Co.
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