Multigate semiconductor device with vertical channel current...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S275000, C438S270000

Reexamination Certificate

active

06677204

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of nonvolatile memories and more specifically to a multibit nonvolatile memory and its method of fabrication.
2. Discussion of Related Art
As integrated circuits and computers have become powerful, new applications have arisen that require the ability to store large amounts of data. Certain applications require a memory with the ability to write and erase data and the ability to store data in a nonvolatile manner. Presently, such memories are formed with electrically erasable nonvolatile memories such as flash devices and EEPROMS. Unfortunately, these devices that are formed in the same plane and therefore require input/outputs (I/Os) which also run in the same plane. Having a source and drain input/output conductors running in the same plane, significantly reduces the number of devices that can be fabricated in a single plane and thereby significantly reduces the storage capability of the memory.
What is desired is a nonvolatile memory device which can be easily fabricated in a dense array, so that large amounts of data can be stored in a nonvolatile manner.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.
According to a second aspect of the present invention, a transistor is provided that has a source, a channel, a drain, and a plurality of gates where the channel current flows vertically between the source and drain.
According to a third embodiment of the present invention, a memory element is formed using a transistor that has a read current that flows in a direction perpendicular to a substrate in or over which the transistor is formed. The transistor has a charge storage medium for storing its state. Multiple control gates address the transistor.


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