Multicore processor test method

Details Multicore processor test method Multicore processor test method

2008-04-01

2008-04-01

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10967280

ABSTRACT:
In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

REFERENCES:
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6954886 (2005-10-01), Tu et al.
patent: 7139947 (2006-11-01), Miner et al.
patent: 2004/0006729 (2004-01-01), Pendurkar

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