Multichip leadframe package

Details Multichip leadframe package Multichip leadframe package

2007-03-14

2008-10-14

Clark, S. V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S676000

Reexamination Certificate

active

07436048

ABSTRACT:
A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first die is attached to a first side of the leadframe die paddle. The second side of the leadframe is partially cut away so that an outer part of the die paddle is thinner, and an inner part of the leads is thinner. These partially cutaway portions in the second side of the leadframe provide a cavity, in which a second die is attached active side upward. The lower die may have bond pads near the center of the active surface, and electrical interconnection of the lower die may be made by wire bonds running through the gap between the die paddle and the leads; or, the lower die may be attached, and electrically interconnected, by flip chip interconnect to the die attach side of the cavity in the leadframe.

REFERENCES:
patent: 6707151 (2004-03-01), Noguchi
patent: 7005325 (2006-02-01), Chow et al.
patent: 2002/0145180 (2002-10-01), Terui et al.
patent: 2003/0001252 (2003-01-01), Ku et al.
patent: 2003/0042591 (2003-03-01), Goller et al.
patent: 2003/0214023 (2003-11-01), Uchida

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