Multi-step chemical mechanical polishing of a gate area in a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S279000, C438S157000

Reexamination Certificate

active

07125776

ABSTRACT:
A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

REFERENCES:
patent: 6162368 (2000-12-01), Li et al.
patent: 6350693 (2002-02-01), Chang et al.
patent: 6431959 (2002-08-01), Mikhaylich et al.
patent: 6458662 (2002-10-01), Yu
patent: 6855607 (2005-02-01), Achuthan et al.
patent: 2005/0029603 (2005-02-01), Yu et al.
patent: 199 32 829 (2001-01-01), None
patent: 2001-319900 (2000-05-01), None
patent: 2002-231662 (2001-01-01), None
Hayashi et al., A New Two-Step Metal-CMP Technique for a High Performance Multilevel Interconnects Featured by Al-and Cu in Low Epsilon Organic Film' Metallizations , 1996 Symposium on VLSI Technology. Digest of Technical Papers, Honolulu, Jun. 11-13, 1996, Symposium on VSLI Technology. Digest of Technical Papers, New York, IEEE, US, Jun. 11, 1996, pp. 88-89, XP000639297.
International Search Report dated Jan. 14, 2005, for International Application No. PCT/US2004/017724.
Digh Hisamoto et al.: “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al.: “Sub-20nm CMOS Fin FET Technologies,” 0-7803-5410-9/99 IEEE, Mar. 2001, 4 pages.
Xuejue Huang et al.: “Sub-50 nm P-Channel Fin FET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yang-Kyu Choi et al.: “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Xuejue Huang et al.: “Sub 50-nm FinFET: PMOS,” 0-7803-7050-3/01 IEEE, Sep. 1999 4 pages.

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