Multi-stage pipelined data coalescing for improved frequency ope

Details Multi-stage pipelined data coalescing for improved frequency ope Multi-stage pipelined data coalescing for improved frequency ope

1998-04-24

2000-02-08

Eng, David Y.

Electrical computers and digital data processing systems: input/

Input/output data processing

Concurrent input/output processing and data transfer

G06F 1300

Patent

active

060237376

ABSTRACT:
To implement full gathering of data transfers from a processor to a system bus without adding many levels of logic to the write enable logic for transaction queue entries or reducing the processor operating frequency, gatherable combinations are divided and gathering is performed in multiple stages operating in parallel. During the first stage, a subset of the full gathering is performed between incoming transactions and the last transaction received, coalescing the two transfers into a single transaction entry if one of the possible combinations within the subset is satisfied. During the second stage, existing queue entries are tested for the remainder of the full gather combination set and merged if a combination within the remaining subset is satisfied. The gathering logic may thus be split between the write enable logic and the entry control logic for the transaction queue, reducing the depth of logic required for any one path and increasing the set size of gatherable combinations implemented and/or the processor operating frequency. Any additional processor cycles required to complete full gathering are typically hidden by bus latency.

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