Multi-stage data processor with signal repeater

Details Multi-stage data processor with signal repeater Multi-stage data processor with signal repeater

2011-04-05

2011-04-05

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

07921344

ABSTRACT:
A signal processing device having a plurality of processing stages, each of the plurality of processing stages being adapted for applying an input signal to each of at least one item under examination to be coupled to a respective one of the plurality of processing stages, and at least one signal reconditioning unit, each of the at least one signal reconditioning unit being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages and a subsequent one of the plurality of processing stages.

REFERENCES:
patent: 6028439 (2000-02-01), Arkin et al.
patent: 7743304 (2010-06-01), Volkerink et al.
patent: WO 99/23499 (1999-05-01), None
Rochit Rajsuman, “An Overview of the Open Architecture Test System”, Second IEEE International Workshop on Electronic Design, Test and Applications, Feb. 2004, pp. 1-6.
International Search Report dated Oct. 31, 2006 from PCT/EP2006/050727.

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