Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-06-28
2004-02-10
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S624000, C438S701000
Reexamination Certificate
active
06689695
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of dual damascene patterning using a multi-purpose composite mask.
(2) Description of the Related Art
In forming dual a damascene structure, via protection is important especially in using the via-first approach, which is explained more in detail below. In this via-first (or, counter-bore) approach, the typical via protection materials are organic, such as photoresist or anti-reflection coating (ARC). It is usually difficult to have a conformal filling of the via with this type of filler materials, especially for small geometry features where consistent filling height is sought. In addition, these organic materials react with the outgassing that occurs from the sidewalls of the vias, thus causing via poisoning. It is disclosed later in the embodiments of the present invention a method of alleviating these via filling problems.
The term ‘damascene’ is derived from a form of inlaid metal jewelry. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, trenches and holes in appropriate locations in the trenches are formed in an insulative material by etching, which are then filled with metal. Metal in trenches form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or trenches, are formed in an insulative layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the trenches of a single damascene, hole openings are also formed at appropriate places in the trench further into the insulative layer. The resulting composite structure of trenches and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process shown in
FIG. 1
a,
two insulative layers (
120
) and (
130
), sometimes referred to as intermetal dielectrics (IMD), are formed on a substrate (
100
) with an intervening etch-stop or trench-stop layer (
125
). Substrate (
100
) is provided with metal layer (
110
) and another etch-stop layer or via-stop liner (
115
). Metal layer can be the commonly used aluminum or copper, while the liner can be another dielectric layer. A desired trench or trench pattern (
150
) is first etched into the upper insulative material (
130
) using conventional photolithographic methods and photoresist (
140
). The etching stops on trench-stop layer (
125
). Next, a second photoresist layer (
160
) is formed over the substrate, thus filling the trench opening (
150
), and patterned with hole opening (
170
), as shown in
FIG. 1
b.
The hole pattern is then etched into the lower insulative layer (
120
) as shown in
FIG. 1
c
and photoresist removed, thus forming the dual damascene structure shown in
FIG. 1
f.
Or, the order in which the trench and the hole are formed can be reversed so that the hole is formed first, which is called the “via-first” process. The fact that the trench is formed later over the hole, the process is sometimes referred to as “counter-bore” as in forming a counter-bore for a screw. Thus, the upper insulative layer (
130
) is first etched, or patterned, with hole (
170
), as shown in
FIG. 1
d.
The hole pattern is also formed into etch-stop layer (
125
). Then, the upper layer is etched to form trench (
150
) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (
120
), as shown in
FIG. 1
e.
It will be noted that trench-stop layer (
125
) stops the etching of the trench into the lower insulation layer. Similarly, via-stop layer (
115
) also stops etching. However, layer (
115
) at the bottom of opening (
170
) is removed before metal is deposited at the next step. Thus, after the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (
180
), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in
FIG. 1
f.
In prior art, various methods of forming damascene structures are described. In U.S. Pat. No. 6,074,942, Lou describes a method for forming a dual damascene contact and interconnect with the steps of: forming an insulating layer on a substrate; forming a nitride layer over said insulating layer; forming a cap oxide layer over said nitride layer; patterning and etching said insulating layer, nitride layer, and cap oxide layer to correspond to the location of said contacts; patterning and etching said nitride layer and said cap oxide layer to correspond to the pattern of said interconnects; and performing a reflow step.
In U.S. Pat. No. 6,083,822, Lee discloses a fabrication process for a copper dual damascene structure where a composite insulator layer, comprising silicon oxide layers, and multiple silicon nitride layers as stop layers are used. A method of forming a self-aligned dual damascene structure is described by Wang, et al., in U.S. Pat. Nos. 6,207,576 and 6,207,577. A nitride etch stop layer is formed on an oxide layer on a substrate, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by over etching is prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.
In another U.S. Pat. No. 6,042,999 by Line, et al., a robust damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In a first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need for an etch-stop layer.
A dual damascene with a sacrificial via fill is described in U.S. Pat. No. 5,705,430 by Avanzino, et al. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching. The sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings.
A method for making
Lui Meng-Huei
Sung Mei-Hui
Ackerman Stephen B.
Everhart Caridad
Saile George O.
Schnabel Douglas R.
Taiwan Semiconductor Manufacturing Company
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