Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-12-28
1999-02-23
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711117, 711118, 711120, 711121, 711122, 711141, 711143, 711144, 711145, 711146, 711137, 711154, G06F 1300, G06F 1208
Patent
active
058754628
ABSTRACT:
A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processors. Each of the second-level caches is coupled to the other second-level cache, coupled to the main storage, and coupled to predetermined ones of the first-level caches. The range of cacheable addresses for both of the second-level caches encompasses the entire address space of the main storage. Each of the second-level caches may be viewed as dedicated for write access to the set of processors associated with the predetermined set of first-level caches, and shared for read access to the other set of processors. The dedicated and shared nature enhances system efficiency. The cache architecture includes coherency control that filters invalidation traffic between the second-level caches. The filtering of invalidation traffic enhances system efficiency and is accomplished by tracking which second-level cache has the most recent version of the cached data.
REFERENCES:
patent: 4442487 (1984-04-01), Fletcher
patent: 4445174 (1984-04-01), Fletcher
patent: 4513367 (1985-04-01), Chan et al.
patent: 4586133 (1986-04-01), Steckler
patent: 4755930 (1988-07-01), Wilson et al.
patent: 4985829 (1991-01-01), Thatte
patent: 5023776 (1991-06-01), Gregor
patent: 5029070 (1991-07-01), McCarthy
patent: 5265232 (1993-11-01), Gannon
patent: 5265235 (1993-11-01), Sindhu
patent: 5276848 (1994-01-01), Gallagher
patent: 5307477 (1994-04-01), Taylor
patent: 5317716 (1994-05-01), Liu
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5355467 (1994-10-01), MacWilliams
patent: 5359723 (1994-10-01), Mathews
patent: 5386547 (1995-01-01), Jouppi
patent: 5392416 (1995-02-01), Doi
patent: 5423016 (1995-06-01), Tsuchiya
patent: 5426754 (1995-06-01), Grice et al.
patent: 5530832 (1996-06-01), So et al.
patent: 5537640 (1996-07-01), Pawlowski et al.
patent: 5603005 (1997-02-01), Bauman et al.
patent: 5625892 (1997-04-01), Bauman et al.
patent: 5671391 (1997-09-01), Knotts
patent: 5684977 (1997-11-01), Van Loo et al.
Balding Mark L.
Bauman Mitchell A.
Englin Donald C.
Johnson Charles A.
McMahon Beth L.
Starr Mark T.
Swann Tod R.
Tran Denise
LandOfFree
Multi-processor data processing system with multiple second leve does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-processor data processing system with multiple second leve, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-processor data processing system with multiple second leve will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-315865