Multi-port SRAM with reduced access requirements

Details Multi-port SRAM with reduced access requirements Multi-port SRAM with reduced access requirements

1998-07-31

1999-09-14

Dinh, Son T.

Static information storage and retrieval

Addressing

Multiple port access

36518902, G11C 800

Patent

active

059532831

ABSTRACT:
An improved multi-port SRAM that requires fewer access means, bit lines and sense amplifiers for multiport access. The number of access means can be reduced to ceiling (log.sub.2 B), where B is the number of access ports. The number of bit line sense amplifiers needed to achieve multiport access can also be reduced by the same factor as the number of access devices per cell. An efficient means is provided to select a correct access device among the plurality of access devices within the array and to condition a correct multiplexer select signal to couple a correct bit as specified by the port read address to the port read output. The access device selection can be implemented by a tree representation of all possible bit line and multiplexer select combinations. The tree representation can be implemented in hardware or software. Examples are provided of both a circuit and a tree walking algorithm that gives priority by port order. Alternatively, logic to select the bit lines and controls could give priority in bit order. In either case, examples are provided for modifying the strict priority order to avoid conflicts and obtain a correct solution.

REFERENCES:
patent: 5177706 (1993-01-01), Shinohara et al.
patent: 5255239 (1993-10-01), Taborn et al.
patent: 5568443 (1996-10-01), Dixon et al.
patent: 5793681 (1998-08-01), Nii
patent: 5877976 (1999-03-01), Lattimore et al.
G. Gerosa et al., "A 2.2 W, 80 Mhz superscalar RISC Microprocessor", IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1440-1454 .

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