Multi-port register implementation

Details Multi-port register implementation Multi-port register implementation

1983-03-10

1985-11-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365174, G11C 1140

Patent

active

045546452

ABSTRACT:
The present invention is especially directed toward a memory cell designed for use in a register stack in which multiple independent and parallel read/write and read operations may proceed simultaneously. The cell comprises multiple write transistors and multiple read transistors all coupled to a single dynamic storage means which can be written into and read from, simultaneously.

REFERENCES:
patent: 3585613 (1971-06-01), Palfi
patent: 3636528 (1972-01-01), Morris
patent: 3979735 (1976-09-01), Payne
patent: 4122547 (1978-10-01), Schroeder et al.
patent: 4125877 (1978-11-01), Reinert
patent: 4193127 (1980-03-01), Gersbach
patent: 4280197 (1981-07-01), Schlig
patent: 4287575 (1981-09-01), Eardley et al.
patent: 4321492 (1982-03-01), Hollingsworth
Electronics Design News, May 1, 1970, "Dynamic MOS", pp. 20, 21.

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