Multi-port memory devices having clipping circuits therein...

Details Multi-port memory devices having clipping circuits therein... Multi-port memory devices having clipping circuits therein...

2011-02-22

2011-02-22

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S230060, C365S184000, C365S189060

Reexamination Certificate

active

07894296

ABSTRACT:
An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.

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