Multi-port memory chip in a hierarchical memory

Details Multi-port memory chip in a hierarchical memory Multi-port memory chip in a hierarchical memory

1984-12-31

1986-12-30

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365220, 365230, G11C 1300

Patent

active

046334408

ABSTRACT:
A hierarchical memory system in which a lower level transfers data serially to an upper level and in parallel to a yet lower level. The lower level includes a two-port memory chip having a wide buffer for parallel accesses to the memory array, to the yet lower level, and to a serial buffer. The serial buffer is serially accessed to the upper level simultaneously with accesses to the wide buffer.

REFERENCES:
patent: 4402067 (1983-08-01), Moss et al.
patent: 4489381 (1984-12-01), Lavallee et al.
Matick et al., "All Point Addressable Raster Display Memory", IBM Journal of R&D, vol. 28, No. 4, Jul. 84, pp. 379-392.

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