Multi-port memory cells and memory with parallel data initializa

Details Multi-port memory cells and memory with parallel data initializa Multi-port memory cells and memory with parallel data initializa

1996-11-18

1998-02-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518905, 36523005, G11C 1300

Patent

active

057176388

ABSTRACT:
A static RAM memory cell with a plurality of input/output ports is disclosed including: a latch circuit which maintains complementary voltages at first and second nodes; a first output circuit which generates an output signal having an state inverted from the voltage of the first node; a second output circuit which generates an output signal having an state inverted from the voltage of the second node; a first transfer circuit for transferring the output signals from the first and second output circuits to a first sense amplifier in response to a first read control signal; a second transfer circuit for transferring the output signals from the first and second output circuits to a second sense amplifier in response to a second read control signal; a third transfer circuit for transferring an external voltage to the first node in response to a write control signal; and a reset circuit for resetting the latch circuit to initialize data in response to a reset signal.

REFERENCES:
patent: 5493536 (1996-02-01), Aoki

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