Multi-phase duty-cycle corrected clock signal generator and...

Details Multi-phase duty-cycle corrected clock signal generator and... Multi-phase duty-cycle corrected clock signal generator and...

2011-01-18

2011-01-18

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233110, C365S194000, C365S230060

Reexamination Certificate

active

07872924

ABSTRACT:
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.

REFERENCES:
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patent: 7106655 (2006-09-01), Lee
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patent: 2010/0085094 (2010-04-01), Ma
patent: 2010/0085099 (2010-04-01), Ma
Ki-Won Lee et al.; “A 1.5-V 3.2 Gb/s/pin Graphic DDR4 Sdram With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL”; IEEE Journal of Solid-State Circuits, vol. 42; No. 11; Nov. 2007; pp. 2369-2377.

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