Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-04-17
2004-04-27
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S480000, C438S413000
Reexamination Certificate
active
06727125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to the fabrication of thin film transistors (TFTs) for liquid crystal displays (LCDs) and, more particularly, to a system and method for using a shadow mask for the laser annealing of silicon substrates, to form precisely located polysilicon or single crystal active regions.
2. Description of the Related Art
The TFTs used in LCD active layer are made from either polycrystalline or single grain crystalline silicon (Si) films that are crystallized in response to laser annealing an amorphous silicon precursor film. These TFTs are used to form pixel switching devices, and/or LCD peripheral circuits, and/or electro-luminescence displays. They are also used in the fabrication of various integrated circuits like sensor arrays on a glass substrate.
A major industrial application of poly-Si thin film transistors (TFT) is LCD panels with driver circuit integration on the substrates. The quality of poly-Si (polycrystallized silicon) film that is the semiconductor layer of the transistors is one of the most important factors in the formation of TFTs, and directly affects the circuit performance. Poly-Si films typically consist of crystal grains and boundaries between the grains. The grains often include crystal defects. One approach for the improvement of the poly-Si film quality is in the use of a laser annealing method that can crystallize amorphous silicon precursor into a poly-Si film with fewer intra-grain defects.
High-performance TFTs require high electron mobility through the transistor channel region. One TFT fabrication problem is in the control of these channel locations on the substrate. That is, the channels must be located in predetermined substrate areas that are formed from either polycrystalline of single crystal material. Likewise, the orientation, or “direction” of the transistor channel is important when fitting the channel regions inside polycrystalline regions.
As a next generation laser annealing technology, a laser induced lateral growth crystallization technique is described in U.S. Pat. No. 6,322,625 (Im). This technology features the seed area of the film being localized by laser beam irradiation, defined through a patterned projection mask that is a shadow mask. Localized solidification occurs laterally from the seed area. By the use of this technique, the quality of the localized area in the poly-Si film is improved. Along the direction of lateral growth, the grain boundaries can be reduced dramatically. However, in the perpendicular direction the grain boundaries are likely to be degraded even further. Therefore, the best performing TFTs have channel regions are formed in the localized high quality poly-Si area, with channels formed in a direction parallel to the lateral growth. Using this process, a semiconductor material having regular, quasi-regular, or single-crystal structure can be made by a technique involving localized irradiation of the film with one or several pulses of a beam of laser radiation. A patterned projection mask defines the localized irradiation of the laser beam. The technique can be used in the manufacture of high-speed liquid crystal display devises, wherein pixel switches or/and driver circuitry are made in single-crystal or regular polycrystalline films.
A technique of locating transistor channels in a polycrystalline silicon film is disclosed in U.S. Pat. No. 6,281,470 (Adachi). The active layer of all the semiconductor elements are formed in alternating regions of silicon film having different crystallization characteristics. However, this process has profound limitations as an efficient fabrication procedure.
It would be advantageous if transistor channels could be defined more precisely in predetermined polycrystalline, or single crystal substrate regions.
It would be advantageous if a shadow mask laser annealing process could be used more for more precisely locating transistor channel regions.
SUMMARY OF THE INVENTION
The present invention laser annealing system and method features the use of a shadow mask for the patterned projection of a laser beam. The mask is divided into block patterns called sections. The mask has the capability of making alignment marks for the exposure equipment that permits precision alignment. The mask also permits multi-shot laser irradiation. Because of these features, the present invention laser annealing apparatus is able to supply higher performance TFTs and higher yields. The apparatus can control the location and direction of the localized high quality poly-Si area, to match to the layout design (formation) of the TFT channel regions.
The present invention shadow mask includes a plurality of sections with the different aperture patterns, corresponding the layout design of the poly-Si TFT channel regions. Some aperture patterns are designed to form a seed portion of the poly-Si material that is grown laterally by stepping the position of the laser beam, through the same aperture pattern, across the substrate. Other aperture patterns form an alignment mark that is used by the exposure apparatus to precisely define the location of poly-Si islands and localized high quality poly-Si areas. The irradiation can be done with plurality of shots per at the same substrate position through an area of the patterned projection mask to avoid the defects of the poly-Si film caused by the fluctuation in the power of laser beam.
Accordingly, a multi-pattern shadow mask method is provided for laser annealing, the method comprises: supplying a silicon substrate; supplying a multi-pattern shadow mask with a plurality of aperture patterns; creating substrate alignment marks; with respect to the alignment marks, laser annealing a substrate region in a plurality of aperture patterns; forming a corresponding plurality of polysilicon regions; and, forming a corresponding plurality of transistor channel regions in the plurality of polysilicon regions.
In some aspects of the method, laser annealing in a plurality of aperture patterns includes: laser annealing a first area in a substrate region with a first aperture pattern; and, step-and-repeat laser annealing in a second area, adjacent the first area, in the substrate region. Then, forming a corresponding plurality of polycrystalline regions includes laterally growing crystals in response to the step-and-repeat laser annealing process.
Typically, the shadow mask includes a plurality of sections, with each section having at least one aperture pattern. A shadow mask section can be selected to create a corresponding aperture pattern. If the mask section includes a plurality of aperture patterns, the selection of mask section creates all the corresponding aperture patterns in the selected section.
More specifically, using the shadow mask to create the plurality of aperture patterns includes: selecting a first mask section with a plurality of aperture patterns; using the alignment marks, aligning the substrate with the first mask; using the first mask section to step-and repeat laser anneal regions in the substrate with the plurality of aperture patterns; selecting a second mask section with a plurality of aperture patterns; using the alignment marks, aligning the substrate with the second mask; using the second mask section to step-and repeat laser anneal regions in the substrate with the plurality of aperture patterns. Then, forming polycrystalline regions in a plurality of patterns includes: forming a plurality of polycrystalline patterns in response to laser annealing with the first mask section; and, forming a plurality of polycrystalline patterns in response to laser annealing with the second mask section.
Additional details of the above-described method, a multi-pattern shadow mask, and a multi-pattern shadow mask annealing system are described below.
REFERENCES:
patent: 4667109 (1987-05-01), Kano
patent: 5074667 (1991-12-01), Miyatake
patent: 5083466 (1992-01-01), Holm-Kennedy et al.
patent: 5138176 (1992-08-01), Nishi
patent: 5145432 (1992-09-01), Midland et al.
patent: 5703675
Adachi Masahiro
Voutsas Apostolos T.
Jr. Carl Whitehead
Rabdau Matthew D.
Ripma David C.
Schillinger Laura M
Sharp Laboratories of America Inc.
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