Multi-path accessible semiconductor memory device having...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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C711S149000, C365S230050

Reexamination Certificate

active

07606982

ABSTRACT:
A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.

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Welche Moglichkeiten bieten et al “Speicherkonfigureationen Mit Dual-Port-Srams”, Design & Electronic, Aug. 19, Vom 13.09. 1998, pp. 123 and 125.

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