Multi- node, multi-level cache- only memory architecture with re

Details Multi- node, multi-level cache- only memory architecture with re Multi- node, multi-level cache- only memory architecture with re

1996-07-12

1999-08-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711133, 711148, 364134, G06F 1212

Patent

active

059374314

ABSTRACT:
A data processing apparatus having a memory access architecture which utilizes distributed shared-memory multiprocessors, and relates more particularly to a non-inclusive memory access mechanism in said architecture. The local memory in each node of shared memory is utilized as a backing store for blocks discarded from the processor cache to delay the address binding to the local memory until the blocks are discarded from the processor cache. Such avoids enforcement of the inclusion property and long latency due to the inclusion property. The invention further provides a method of maintaining coherency in a system which utilizes a distributed shared-memory multiprocessors architecture.

REFERENCES:
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4939641 (1990-07-01), Schwartz et al.
patent: 5274787 (1993-12-01), Hirano et al.
patent: 5377345 (1994-12-01), Chang et al.
patent: 5394555 (1995-02-01), Hunter et al.
patent: 5459852 (1995-10-01), Nakagawa et al.
patent: 5535116 (1996-07-01), Gupta et al.
patent: 5564035 (1996-10-01), Lai
patent: 5692149 (1997-11-01), Lee
Norman P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers", 1990 IEEE; pp. 364-373.
Norman P. Jouppi et al., "Tradeoffs in Two-Level On-Chip Caching", 1994 IEEE; pp. 34-45.
Kong, J.; Lee, G. "DYMA: A Novel Memory Architecture for Distributed Shared Memory Multiprocessors", DICE Project Technical Report #14, May 1995. http://www-mount.ee.umn.edu/.about.ghlee/papers.html, Jun. 1995.
Kong, J.; Lee, G. "Relaxing Inclusion Property in Cache Only Memory Architecture." Proceedings of EURO-PAR '96, Lyon, France, Aug. 1996.
Hagersten, E.; Landin, A.; Haridi, S. "DDM--A Cache-Only Memory Architecture." IEEE Computer, vol. 25(9) (Sep. 1992): 44-54.

Affiliated with

Also associated with

Rating

Multi- node, multi-level cache- only memory architecture with re does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi- node, multi-level cache- only memory architecture with re, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi- node, multi-level cache- only memory architecture with re will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1131105