Multi-level split- gate flash memory cell

Details Multi-level split- gate flash memory cell Multi-level split- gate flash memory cell

1997-11-20

1999-03-02

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, 438266, 36518526, H01L 29788

Patent

active

058775234

ABSTRACT:
A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.

REFERENCES:
patent: 5364806 (1994-11-01), Ma et al.
patent: 5414287 (1995-05-01), Hong
patent: 5472892 (1995-12-01), Gwen et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5652447 (1997-07-01), Chen et al.
patent: 5674768 (1997-10-01), Chang et al.

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