Multi-level memory cell utilizing measurement time delay as...

Details Multi-level memory cell utilizing measurement time delay as... Multi-level memory cell utilizing measurement time delay as...

2007-09-18

2009-10-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S203000, C365S204000

Reexamination Certificate

active

07602631

ABSTRACT:
A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.

REFERENCES:
patent: 5654928 (1997-08-01), Lee et al.
patent: 6035365 (2000-03-01), Farmwald et al.
patent: 6597183 (2003-07-01), Male
patent: 6690183 (2004-02-01), Braun
patent: 6816796 (2004-11-01), Bierl
patent: 7061789 (2006-06-01), Nazarian
patent: 7227808 (2007-06-01), Kim
patent: 7453715 (2008-11-01), Parkinson
patent: 2002/0093855 (2002-07-01), Heyne et al.

Affiliated with

Also associated with

Rating

Multi-level memory cell utilizing measurement time delay as... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level memory cell utilizing measurement time delay as..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level memory cell utilizing measurement time delay as... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4125858