Multi-level dynamic memory device

Details Multi-level dynamic memory device Multi-level dynamic memory device

2009-02-02

2010-11-16

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S069000, C365S205000, C365S206000, C365S210120, C365S210130

Reexamination Certificate

active

07835208

ABSTRACT:
A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.

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