Electronic digital logic circuitry – Three or more active levels – With conversion
Reexamination Certificate
2006-05-30
2006-05-30
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Three or more active levels
With conversion
C326S059000, C375S286000
Reexamination Certificate
active
07053655
ABSTRACT:
An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of ΔV, includes a plurality of field effect transistors for driving the output by supplying or removing a current to or from the output, with the relationship of the channel widths of at least two field effect transistors, which both function either to lead a current to or away, being set in dependence on the value of the voltage difference.
REFERENCES:
patent: 6140841 (2000-10-01), Suh
patent: 6292014 (2001-09-01), Hedberg
patent: 6339622 (2002-01-01), Kim
patent: 198 25 258 (1999-12-01), None
Author not listed: “EIA/JEDEC Standard; Stub Series Terminated Logic for 3.3 Volts (SSTL—3)”, Electronic Industries Association, Engineering Department, No. 8-8, Aug. 1996, pp. 1-14.
Cho James H.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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