Multi-layer interconnect structure for semiconductor devices

Details Multi-layer interconnect structure for semiconductor devices Multi-layer interconnect structure for semiconductor devices

2008-05-06

2008-05-06

Sarkar, Asok K. (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S641000, C438S625000, C257S762000, C257SE21586

Reexamination Certificate

active

11197009

ABSTRACT:
An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

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patent: 4620986 (1986-11-01), Yau et al.
patent: 6340633 (2002-01-01), Lopatin et al.
patent: 6368965 (2002-04-01), Lopatin
patent: 2004/0229456 (2004-11-01), Andricacos et al.
patent: 2006/0121725 (2006-06-01), Basol et al.

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