Multi-layer interconnect

Details Multi-layer interconnect Multi-layer interconnect

1999-11-02

2002-05-14

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S759000, C257S760000

Reexamination Certificate

active

06388325

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is multi-layer substrates/interconnects.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) package is a housing which environmentally protects the IC, facilitates testing of the IC, and facilitates the use of the IC in high-yield assembly processes. Such a package functions to protect an IC from mechanical and environmental stresses and electrostatic discharge. It also functions to provide a mechanical interface for testing, burn-in, and interconnection to a higher level of packaging such as a circuit card.
In many IC packages a substrate acts as an interconnecting layer between the terminals or pads on the IC, and the connectors or leads of the package. The substrate is typically mechanically and electrically coupled to both the IC and the package leads. The substrate may be made from a ceramic or organic material, may be rigid or flexible, and may comprise a single layer or multiple layers laminated together.
As IC technology progresses, there is a growing need for higher density interconnecting layers. The process used by the printed circuit board industry to build high density interconnects typically starts with providing a large multi-layered printed circuit board core having 2-6 layers with drilled and plated through holes. Individual parts are stepped and repeated on the core to produce a panel of parts. A high density interconnect (HDI) comprises multiple panels/layers. HDI layers are typically either added sequentially, layer by layer or layers are made individually and then laminated in mass.
Each layer/panel of an HDI generally has good and bad parts. The percentage of the total number of parts which are good is typically specified as percentage yield. For a single panel/layer it is not uncommon to achieve a yield of 90%. However, since each layer has less than 100% yield, and since bad parts tend to be distributed randomly throughout the panel, each layer added to an HDI panel tends to decrease the number of good parts on, and thus the yield of, the panel. Thus, a two layer interconnect comprising two 90% panels may have a yield of 81%, i.e. 81% of the individual parts/cells on the panel are good. A three layer interconnect may have a yield of 73%, four layers 66%, and five layers 60%. This decrease in yield as the number of layers is increased undesirable. Thus, there is a continuing need to develop new forms and new method for producing high density interconnects.
SUMMARY OF THE INVENTION
The present invention is directed to methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new are panels created entirely of the identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.
Various objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention, along with the accompanying drawings in which like numerals represent like components.


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patent: WO 98/26476 (1998-06-01), None

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