Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-02-22
2003-10-28
Le, Don (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S093000, C326S038000
Reexamination Certificate
active
06639422
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits that generate clock signals and, more particularly, to, integrated circuits that generate and utilize multiple clock signals.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) are extensively used in all types of electronic devices and/or systems. One characteristic of an IC's operation is the necessary utilization of a clock signal. The clock signal has particular frequency and determines, at least in part, the processing, execution, or state change speed of the IC. The clock signal may be provided to the IC from an external source or it is may be generated internally. When the clock signal is provided by an external source, it is of a particular frequency depending on the design characteristics of the particular IC. When the clock signal is generated internally, typically an external clock signal of a base frequency is provided to the IC which then converts the external clock signal of the base frequency into another usable clock signal frequency. Most ICs, however, utilize only one clock signal.
However, certain ICs used in electronic systems may require multiple clock signals to function properly. The multiple clock signals are typically generated on the IC from a single, externally generated clock signal input, rather than receiving multiple, externally generated clock signals. This reduces this number of pins/terminals on the IC for input clock signals which is important in integrated circuit design. An exemplary multiple clock IC as described above, known as a Universal Link IC, is used in a DTV-320 HDTV (High Definition Television) being developed by Thomson Consumer Electronics, Inc. of Indianapolis, Ind. The Universal Link IC may be used in other television signal processing devices.
The Universal Link IC is a mixed signal design (i.e. uses analog and digital signals) that integrates several signal processing functions. In general, the Universal Link IC contains a section for demodulating satellite signals, a section for demodulating HDTV signals, and a section that provides switching and chroma demodulation and other signal processing of NTSC television signal inputs. Each one of these sections requires a different clock frequency (i.e. a different clock signal). Other portions of the Universal Link IC may require even different clock signals. The Universal Link IC thus generates multiple clock signals as required for the various sections of the IC from a single, externally generated clock signal input via a clock input pin. In addition to the clock input pin, typical multiple clock ICs have an observation pin dedicated to each generated clock signal and a test pin dedicated to each generated clock signal.
Although multiple clock signals are necessary in some ICs, it is desirable to minimize the number of I/O (Input/Output) pins or terminals of the IC that are dedicated to clock generation, observation and testing thereof. This is because the number of available pins on an IC are limited and are usually needed for many other functions. However, it is also desirable to provide both observability of the internal clock signals being generated, e.g. for debugging purposes, and controllability of the clock signals, e.g. for testing purposes. Thus, there is contention between the number of available I/O pins for all of the needed IC functions and the need to reduce that number of I/O pins while retaining the functionality. External controllability is also desired since a Phase Locked Loop (PLL) synthesizer generally used in the internal generation of the various IC clock signals, is an analog circuit block.
What is therefore needed is a system, apparatus, and method that reduces the number of I/O pins for various aspects of clock functionality in a multiple clock IC.
What is further needed is a system, apparatus, and method that provides for both the minimization of the number of I/O pins dedicated to clock signals and adequate test capabilities of a multiple clock IC.
SUMMARY OF THE INVENTION
The present invention is an apparatus, system and method that has a single, bi-directional clock I/O pin for each internally generated clock signal of a multiple clock IC, with the functionality of each bi-directional clock I/O pin controllable to allow various modes of operation. Mode control of the clock I/O pins is preferably achieved via I
2
C registers in communication with an I
2
C bus/protocol system and a further I/O select pin.
The present invention allows for a normal mode of operation of the clocks, a debugging mode of operation for observation of the internal IC clocks, and/or a test mode of operation to drive the internal IC clock from the pin through the respective bi-directional I/O pin.
The present invention is useful for both digital testing of the IC (when precise control over the test clock phase and timing is important) and for debugging. For example, if the PLL synthesizer was non-functional, an external clock signal may be introduced in place of the normal internally generated clock signal. Thus, IC evaluation is possible even though the PLL may be inoperative.
Mode control of the clock I/O pins is controlled via control bits stored in the I
2
C register. In one embodiment, the register storing the control bits is coupled to a bus, such as an I
2
C serial bus and a bus master or slave sets the control bits by writing data to the register. The register may be memory mapped into the memory address space of the bus master device.
All of the modes of the IC clock signals are independently controllable. In particular, the three modes of operation of the clock I/O pins are: 1) Normal Mode—no internal clocks signal are output on the pins. If the IC is running properly, no clocks will be output on the respective I/O pin. The PLL and clock generator/divider will provide the plurality of internal IC clocks. It is also undesirable from an RFI standpoint to output clocks if not necessary so the clocks are not output on the I/O pads during normal operation.; 2) Test Mode—the PLL/clock generator/divider are bypassed and external test clock(s) are introduced onto the plurality of clock I/O pins. The I/O pins are acting as inputs. This allows full control of the clocks, since they are generated external to the IC and input into the IC.; and 3) Debug Mode—the internal clocks are output onto the plurality of clock I/O pins for observation. This mode is used to assess proper functionality of the PLL/clock generator/divider circuits.
The present invention is advantageous in that minimal IC I/O pins are required (i.e. only one I/O pin per internally generated clock). Further, the present invention allows either internally generated clocks (clock signals) or external clocks (clock signals) to clock the IC. Yet further, the present invention make it possible to observe internal clocks on the same set of I/O pins. Additionally, the present invention makes it possible to provide for automatic detection of mode of operation (e.g. test mode vs. normal functional mode of operation, and switch accordingly as disclosed in U.S. Pat. No. 5,517,109 entitled “Apparatus within an integrated circuit for automatically detecting a test mode of operation of the integrated circuit and selecting a test clock signal” by Albean el al., issued May 14, 1996, which is hereby specifically incorporated into the present specification by reference. Still further, the present invention
In one form, the present invention is an apparatus in an integrated circuit. The apparatus includes a pin for coupling signals to and/or from the integrated circuit, a clock signal generator internal to the integrated circuit for producing a first clock signal, switching means responsive to a control signal, and control means for generating the control signal. The switching means is responsive to the control signal for providing: 1) a first mode of operation during which the first clock signal is utilized by a device internal to the integrated circuit and during which the first clock signal is not provided to the pin; 2) a second mode of operati
Le Don
Shedd Robert D.
Thomson Licensing S.A.
Tripoli Joseph S.
LandOfFree
Multi-clock integrated circuit with clock generator and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-clock integrated circuit with clock generator and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-clock integrated circuit with clock generator and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3167771