Multi-chip semiconductor package structure

Details Multi-chip semiconductor package structure Multi-chip semiconductor package structure

2001-02-20

2002-10-01

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Physical stress responsive

C438S055000, C438S108000, C438S123000

Reexamination Certificate

active

06458617

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89126688, filed Dec. 14, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a multi-chip liquid semiconductor package structure and its method of manufacture. More particularly, the present invention relates to a duplicate chip, duplicate conductive wire package structure capable of shrinking overall package volume while increasing package reliability.
2. Description of Related Art
In this information explosion age, electronic products have enjoyed a close relationship with everybody in this society. Following the rapid progress in electronic technologies, electronic products have become lighter, smaller and more portable. In addition, most electronic products can provide highly personalized functions at an affordable price. Market forces are now pushing semiconductor manufacturers towards manufacturing packages having higher device density to volume ratio. One recent advance of package structure design is the introduction of multi-chip package.
FIG. 1
is a schematic cross-sectional diagram of a conventional lead-on-chip (LOC) chip-stack package structure. The LOC chip-stack package structure shown in
FIG. 1
is disclosed in U.S. Pat. No. 5,701,031. The conventional lead-on-chip chip-stack package
100
in
FIG. 1
has two chips, including a first chip
130
and a second chip
160
, enclosed within a package material
102
. The active surface
132
of the first chip
130
and the active surface
162
of the second chip
160
are facing each other. The package
100
also has two lead frames, a first lead frame
134
and a second lead frame
164
. The first lead frame
134
includes a plurality of inner leads
136
and a plurality of outer leads
138
. The second lead frame
164
has a plurality of inner leads
166
and a plurality of joint sections
168
. The inner leads
136
and
166
are attached to the first chip
130
and the second chip
160
via adhesive tapes
140
and
170
respectively. Through wire bonding, the inner leads
136
and the inner leads
166
are electrically connected to the first chip
130
and the second chip
160
respectively by metallic wires
142
and
172
. The packaging material
102
encloses the first chip
130
, the second chip
160
, the inner leads
136
and
166
, the joint sections
168
, the adhesive tapes
140
and
170
, and the metallic wires
142
and
172
. To form the package
100
, the first chip
130
and the second chip
160
are attached to the first lead frame
134
and the second lead frame
164
using the adhesive tapes
140
and
170
respectively. Wire bonding is next carried out using a bonding machine. Ultimately, the inner leads
136
and the inner leads
166
are electrically connected to the first chip
130
and the second chip
160
respectively by metallic wires
142
and
172
. The leads of the second lead frame
164
are next aligned with the leads in the first lead frame
134
. Using a YAG laser beam, redundant portion of the joint sections
168
are cut away, and at the same time, the joint sections
168
and corresponding contact points on the first lead frame
134
are welded together. The structure is enclosed with plastic in a molding operation. Finally, dam bars (not shown) on the first lead frame
134
are removed following by the bending of external leads
138
.
In the above package, the active surfaces of the two chips are facing each other and hence their respective metallic wires are on the same side. Under such circumstances, contact between a wire on one chip with a neighboring wire on another chip is highly probable and may lead to short-circuiting. A means to prevent short-circuiting is to increase chip separation. However, this will increase the overall package volume and packaging cost. Moreover, using YAG laser to joint the second lead frame
164
onto the first lead frame
134
is an expensive undertaking likely to increase production cost.
FIG. 2
is a schematic cross-sectional diagram of another conventional lead-on-chip (LOC) chip-stack package structure. The LOC chip-stack package structure shown in
FIG. 1
is disclosed in U.S. Pat. No. 5,804,874. The lead-on-chip chip-stack package
200
in
FIG. 2
also has two chips, including a first chip
230
and a second chip
260
embedded within a packaging material
202
. The active surface
232
of the first chip
230
and the active surface
262
of the second chip
260
are both facing up. The package
200
has two lead frames, including a first lead frame
234
and a second lead frame
264
. The first lead frame
234
has a plurality of inner leads
236
and a plurality of outer leads
238
. The second lead frame
2
64
has a plurality of inner leads
266
and a plurality of joint sections
268
. The inner leads
236
and the inner leads
266
are attached to the first chip
230
and the second chip
260
through adhesive tapes
240
and
270
respectively. The inner leads
236
and the inner leads
266
are electrically connected to the bonding pads
244
and
274
on the first chip
230
and the second chip
260
respectively by metallic wires
242
and
272
. The packaging material
202
encloses the first chip
230
, the second chip
260
, the inner leads
236
and
266
, the adhesive tapes
240
,
270
,
276
and
204
, and the metallic wires
242
and
272
. The purpose of putting additional adhesive tape
204
is to increase distance of separation between the lead
242
and the second chip
260
so that probability of electrical contact between the two is minimized. To form the package
200
, the first chip
230
and the second chip
260
are attached to the first lead frame
234
and the second lead frame
264
using the adhesive tapes
240
and
270
respectively. Wire bonding is next carried out using a bonding machine. Ultimately, the inner leads
236
and the inner leads
266
are electrically connected to the bonding pads
244
and
274
on the first chip
230
and the second chip
260
respectively by metallic wires
242
and
272
. The leads of the second lead frame
264
are next aligned with the leads of the first lead frame
234
. The joint sections
268
of the second lead frame
264
are electrically connected to the first lead frame
234
. The structure is enclosed with plastic in a molding operation. Finally, dam bars (not shown) on the first lead frame
234
are removed following by the bending of external leads
238
.
In the above package structure, quite a few adhesive tapes are used. Since adhesive tapes have intrinsic tendency to absorb moisture at the processing stage, frequency of delamination of the package may intensify leading to a lower yield and reliability problem. Thus, the product may subsequently be damaged. Furthermore, short-circuiting between the lower metallic wires and the upper chip is prevented by putting up thick adhesive tapes. Ultimately, overall volume of the package will increase leading to an increase in production cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a multi-chip semiconductor package structure capable of reducing circuit space and enclosing more chips within a given plastic mold, thereby lowering production cost.
A second object of the invention is to provide a multi-chip semiconductor package structure capable of preventing unwanted contact between a conductive wire attached to an upper chip and another conductive wire attached to a lower chip. Hence, device failure due to short-circuiting is avoided.
A third object of the invention is to provide a multi-chip semiconductor package structure capable of preventing unwanted contact between an upper chip and the conductive wire attached to a lower chip, thereby lowering production cost and increasing yield.
A fourth object of the invention is to provide a method of manufacturing a multi-chip semiconductor package capable of using fewer and simpler manufacturing steps so that production cost can be lowered.
A fifth object of the inven

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