Multi-chip semiconductor package and fabrication method thereof

Details Multi-chip semiconductor package and fabrication method thereof Multi-chip semiconductor package and fabrication method thereof

2006-08-15

2006-08-15

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

C257S777000, C257S723000, C257S787000

Reexamination Certificate

active

07091623

ABSTRACT:
A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.

REFERENCES:
patent: 6353263 (2002-03-01), Dotta et al.
patent: 6521881 (2003-02-01), Tu et al.

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