Multi-chip semiconductor package

Details Multi-chip semiconductor package Multi-chip semiconductor package

2001-12-03

2004-01-20

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S666000, C257S692000, C257S778000, C257S787000, C438S106000, C438S126000, C438S127000

Reexamination Certificate

active

06680531

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package in which a chip carrier having a plurality of downwardly extending portions is used, in place of a die pad, to accommodate a semiconductor chip thereon.
BACKGROUND OF THE INVENTION
In response to a trend in profile miniaturization of electronic products, semiconductor devices are desirably made with reduction of costs, high performance and compactness in size. Accordingly, several small-scale semiconductor packages are developed, for example, a TSOP (thin small outline package), SSOP (shrink small outline package) or TQFP (thin quad flat package) is dimensioned in thickness of only 1 mm, and even a UTSOP (ultra thin small outline package) is merely 0.75 mm thick. Further, a semiconductor package is preferably incorporated with two or more semiconductor chips, so as to enhance its integrated circuit density, memory capacity and processing speed.
U.S. Pat. No. 5,527,740 discloses a multi-chip thin semiconductor package. As shown in
FIG. 1
, this conventional semiconductor package
1
employs a lead frame
10
, in which an adhesive layer
11
is formed on each of front and back sides
100
,
101
of a die pad
102
of the lead frame
10
, allowing a first chip
12
and a second chip
13
to be mounted on the back and front sides
101
,
100
of the die pad
102
, respectively. A plurality of first gold wires
14
and second gold wires
15
are used to electrically connect the first and second chips
12
,
13
to leads
103
positioned around the die pad
102
. And an encapsulant
16
is formed to encapsulate the first chip
12
, the second chip
13
, the gold wires
14
,
15
and partially the leads
103
, so as to prevent chip surfaces from being damaged by external moisture and contaminant.
In such a conventional lead-frame based semiconductor package, the die pad
102
is designed correspondingly to predetermined chip dimensions. As shown in
FIG. 2
, during a molding process, a melted molding resin
16
(designated by the same numeral as the encapsulant
16
) is injected into an encapsulating mold
19
. A mold flow of the molding resin
16
is impeded when flowing to the die pad
102
and the first and second chips
12
,
13
mounted on the die pad
102
, and diverted into an upper mold flow
17
and a lower mold flow
18
, wherein the upper mold flow
17
passes the second gold wires
15
, the second chip
13
and an upper mold cavity
192
of the encapsulating mold
19
, while the lower mold flow
18
goes through the first gold wires
14
, the first chip
12
and a lower mold cavity
193
of the encapsulating mold
19
; this then entirely encapsulates the die pad
102
and the first and second chips
12
,
13
in the encapsulant
16
. However, in response to miniaturization in package profile (i.e. reduction in mold cavity height of the encapsulating mold
19
), the foregoing semiconductor package
1
generates several problems. First, the encapsulant
16
of the semiconductor package
1
decreases in thickness due to height reduction of mold cavities
192
,
193
; this deteriorates mechanical strength of the encapsulant
16
, and possibly results in delamination occurring at interfaces among the chips
12
,
13
, the die pad
102
and the encapsulant
16
formed on the chips
12
,
13
due to differences in coefficients of thermal expansion during a temperature cycle in subsequent fabrication processes, so that quality and reliability of fabricated products are seriously degraded.
On the other hand, when overall height H of the mold cavities
192
,
193
is reduced to 1 mm or even to 0.75 mm (as used for the above UTSOP semiconductor package), after combined thickness including the first and second chips
12
,
13
, the adhesive layers
11
,
11
formed on the front and back sides
100
,
101
of the die pad
102
and the die pad
102
itself, is subtracted from the overall height H, it can be calculated from the below equation that a gap left in each of the mold cavities
192
,
193
is only 8 mils wide in average (one mil equals to one thousandth of an inch) for allowing the upper mold flow
17
or the lower mold flow
18
to pass therethrough. The equation is illustrated as follows:
[1−(0.2×2+0.03×2+0.13)]/2=0.205(
mm
) (this is approximately equal to 8
mils
),
wherein the overall height H of the mold cavities is 1 mm, a single chip is 0.2 mm thick, a single adhesive layer is 0.03 mm thick, and the die pad is 0.13 mm in thickness.
As only the 8-mil gap is left between a top surface of the mold cavity and the chip for allowing the mold flow to go therethrough, such a gap is actually the minimal space permeable for the mold flow, and thus it often results in voids in encapsulant
16
due to incomplete filling with the molding resin or air left in the mold cavity. In
FIG. 2
in case of the gold wires
14
,
15
having wire loop height of 6 mils, then a gap “s” between wire loops and the mold cavity for allowing the mold flow to go therethrough can only be 2 mils wide. Such a gap is so narrow and difficult to be permeated by the mold flow, and unbalanced speed of upper and lower mold flows
17
,
18
easily result in die pad floating, thereby making the first gold wires
14
exposed to the outside of the encapsulant
16
, as indicated by the dotted-line circle in FIG.
2
.
In addition, U.S. Pat. No. 5,793,108 discloses another multi-chip thin semiconductor package with stacked chips mounted on a front side of a die pad. As shown in
FIG. 3
, this semiconductor package
1
′ is fabricated in a manner that, a first chip
12
′ is attached onto a die pad
102
′ with its front surface (circuit surface) facing downwardly, and then a second chip
13
′ is stacked on a back surface of the first chip
12
′. The first and second chips
12
′,
13
′ are both dimensionally larger than the die pad
102
′, so as to reduce contact area between the chip
12
′ and the die pad
102
′. Subsequently, after the chips
12
′,
13
′ are electrically connected to a plurality of leads
103
′ positioned around the die pad
102
′ by means of gold wires
14
′,
15
′, an encapsulant
16
′ is formed to encapsulate the first chip
12
′, the second chip
13
′, the gold wires
14
′,
15
′, and the die pad
102
′; this then completely fabricates the multi-chip semiconductor package
1
′.
However, such a semiconductor package
1
′ also has similar problems or drawbacks as the above semiconductor package
1
disclosed in U.S. Pat. No. 5,527,740. Referring to
FIG. 4
, in order to provide more space for accommodating chips without altering the package profile, the semiconductor package
1
′ has the die pad
102
′ positioned lower in elevation than a plane formed by the leads
103
′. Such an arrangement however significantly narrows down a gap between the die pad
102
′ and a lower mold cavity
193
′ for allowing a mold flow to pass therethrough, and thereby makes a lower mold flow
18
′ that goes through the narrowed gap move much slower than an upper mold flow
17
′. Then, the upper mold flow
17
′ rapidly encapsulates the chip
13
′, and generates a downward pressure that presses the die pad
102
′; this results in die pad floating and undesirably makes the gold wires
14
′,
15
′ exposed to the outside of the encapsulant
16
′.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a multi-chip thin semiconductor package, in which a chip carrier with a plurality of downwardly extending portions is used, in place of a die pad, for accommodating semiconductor chips thereon, so as to balance upper and lower mold flows, and prevent die pad floating from occurrence.
Another objective of the invention is to provide a multi-chip thin semiconductor package with a chip carrier having a plurality o

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