Multi-chip package with electrical interconnection

Details Multi-chip package with electrical interconnection Multi-chip package with electrical interconnection

2005-08-09

2005-08-09

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S782000, C257S784000, C257SE23031, C257SE23060, C257SE23145

Reexamination Certificate

active

06927480

ABSTRACT:
A multi-chip package with electrical interconnection comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. A dielectric carrier is attached to the leadframe for fixing the relay conductor. The relay conductor has a top surface for interconnection of the bonding wires and a bottom surface attached to the dielectric carrier to electrically isolated from the leadframe. The bonding wires electrically connect the bonding pads of the first chip and second chip to the common lead of the leadframe through the relay conductor so as to achieve electrical interconnection of the plurality of chips and the leadframe inside the molding compound with lower cost.

REFERENCES:
patent: 5361970 (1994-11-01), Kasai et al.
patent: 5496967 (1996-03-01), Hashimoto et al.
patent: 6759753 (2004-07-01), Chao
patent: TW448518 (2001-08-01), None
patent: 61-237459 (1986-10-01), None
patent: 2-294061 (1990-12-01), None
patent: 4-329661 (1992-11-01), None

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