Multi-chip package structure

Details Multi-chip package structure Multi-chip package structure

2006-12-19

2006-12-19

Kebede, Brook (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S778000, C257S779000, C257SE21503, C257SE21511, C438S107000, C438S108000, C438S613000, C438S612000

Reexamination Certificate

active

07151317

ABSTRACT:
A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

REFERENCES:
patent: 6906415 (2005-06-01), Jiang et al.
patent: 6921968 (2005-07-01), Chung
patent: 2004/0164390 (2004-08-01), Wang

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