Multi-chip package device having alternately-enabled memory...

Details Multi-chip package device having alternately-enabled memory... Multi-chip package device having alternately-enabled memory...

2005-09-19

2009-08-25

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000, C711S105000, C713S002000

Reexamination Certificate

active

07581070

ABSTRACT:
A multi-chip package device includes first and second memory chips configured to share addresses and control signals. The first and second memory chips each include main memory, buffer memory, an option terminal for receiving an option voltage, an access signal generation block, and a controller. The main memory of the first memory chip stores boot code. The buffer memory of the first memory chip includes boot memory. The option voltages of the first and second memory chips have different voltage levels. The access signal generation block generates a buffer access signal that undergoes a one-way transition in response to the boot code address. The one-way transition of the buffer access signal of the first memory chip is a transition to activation, and the one-way transition of the buffer access signal of the second memory chip is a transition to inactivation.

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