Multi-chip package

Details Multi-chip package Multi-chip package

2001-04-19

2004-06-01

Cuneo, Kamand (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

C257S723000, C257S692000

Reexamination Certificate

active

06744121

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-chip package, in particular about a multi-chip package comprising a LOC lead frame.
2. Description of the Related Art
In the past, a common making process of semiconductor devices use a lead frame to support and electrically connect to a semiconductor chip, and then seals the chip with a package body. To achieve higher performance and larger memory capacity, the semiconductor chip has become smaller and more accurate. An idea of stacking and sealing a number of semiconductor chips in the package body during packaging process has also been proposed. A manufacturing process of a multi-chip package has been claimed in the U.S. Pat. No. 5,366,933. As shown in
FIG. 1
, the multi-chip package
10
is used to seal the bottom chip
11
and the upper chip
12
, wherein it comprises a bottom chip
11
, an upper chip
12
, a lead frame, a plurality of bonding wires
16
and
17
, and a package body
18
. This general type of lead frame comprises a plurality of leads
13
and a dice pad
14
. Adhesive films
15
are applied to stick the bottom chip
11
and the upper chip
12
respectively to the bottom and the upper surface of the dice pad
14
. A plurality of bonding wires
16
are further used to connect the bottom chip
11
and the leads
13
by wire-bonding technique, while a plurality of bonding wires
17
are used to connect the upper chip
12
and the leads
13
by wire-bonding technique as well. Because the bottom chip
11
and the upper chip
12
are adhesively stuck to the dice pad
14
with their back surface, an overturn action of the dual chip assembly is necessary during the wire-bonding process. To avoid compressing or scratching the bonding wires
16
during the second wire-bonding process, the manufacture processes of this multi-chip package
10
are in the order of sticking the bottom chip
11
, forming bonding wires
16
to connect the bottom chip
11
and the lead frame, first time of molding and curing (the bottom part of the package body
18
), sticking the upper chip
12
, forming bonding wires
17
to connect the upper chip
12
and the lead frame, second time of molding and curing (the upper part of the package body
18
). Nevertheless, such processes are not widely accepted under taking manufacturing efficiency and cost of molds development into consideration. Another type of multi-chip package is claimed in the U.S. Pat. No. 6,118,176. A LOC lead frame is used to support the upper chip and the bottom chip. The so-called LOC lead frame is the type of lead-on-chip lead frame for short. That is, the leads of the lead frame are extended on the chip for electrical connection and support of the chip without using the dice pad of the lead frame. Such a multi-chip package comprises a dual chip assembly with back-to-back sticking configuration, while the leads of the LOC lead frame are extend on the bottom surface of the bottom chip and fixed with an adhesive film. A circuit board is sticking on the upper surface of the upper chip, so as to enable the bonding wires to electrically connect the upper chip and the circuit board, as well as the circuit board and the leads. Likewise, the manufacture of such a multi-chip package must also involve an overturn action for wire bonding, the bonding wires on the bottom chip, however may be scratched during the wire-bonding process of the upper chip.
SUMMARY OF THE INVENTION
The main object of the present invention is a multi-chop package comprising a LOC lead frame to integrate the upper chip and the bottom chips. The leads of such a LOC lead frame are bend at various places, such that the first inner portion, the supporting portion and the second inner portion are respectively formed on different planes, so as to achieve the effect of packaging the upper and the bottom chip without the needs of overturn for wire-bonding.
In accordance with the multi-chip package in the present invention, it mainly comprises a LOC lead frame, an upper chip, a bottom chip, a plurality of bonding wires, and a package body. The LOC lead frame possesses a plurality of leads, with each lead from inside to outside being divided into the first inner portion, the supporting portion, the second inner portion, and the outer connecting portion. The first inner portion, the supporting portion, and the second inner portion are bent and formed on different planes. The bottom chip has a plurality of bonding pads on its upper surface and the bottom chip is fixed on the first inner portion of the leads of the lead frame with its upper surface. The upper chip possesses a plurality of bonding pads on its upper surface as well, and the upper chip is fixed on the supporting portion of the leads in the lead frame with its bottom surface. A plurality of first bonding wires electrically connect the bonding pads of the bottom chip and the first inner portion of the corresponding leads in the lead frame, while a plurality of second bonding wires electrically connect the bonding pads of the upper chip and the second inner portion of the corresponding leads in the lead frame. Besides, the package body seals the bottom chip, the upper chip, the bonding wires, and the first inner portion, the supporting portion, and the second inner portion of the lead frame.


REFERENCES:
patent: 5332922 (1994-07-01), Oguchi et al.
patent: 5366933 (1994-11-01), Golwalkar et al.
patent: 5545922 (1996-08-01), Golwalkar et al.
patent: 5757080 (1998-05-01), Sota
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 5804874 (1998-09-01), An et al.
patent: 5986335 (1999-11-01), Amagai
patent: 6072243 (2000-06-01), Nakanishi
patent: 6087718 (2000-07-01), Cho
patent: 6118176 (2000-09-01), Tao et al.
patent: 6175149 (2001-01-01), Akram
patent: 6177721 (2001-01-01), Suh et al.
patent: 6225683 (2001-05-01), Yalamanchili et al.
patent: 6252299 (2001-06-01), Masuda et al.
patent: 6255729 (2001-07-01), Oikawa
patent: 6303981 (2001-10-01), Moden
patent: 6316825 (2001-11-01), Park et al.
patent: 6340846 (2002-01-01), LoBianco et al.

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