Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1993-08-26
1994-06-14
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257390, 371 223, 371 226, 365200, H01L 2348, H01L 2346
Patent
active
053212770
ABSTRACT:
A base for a multi-chip module that provides for built-in testability. Active test components are embedded in a module substrate. These test components primarily consist of boundary scan cells that comply with the IEEE 1149.1 test standard. The scan cells are connected to each other, and are connected to interconnection paths among chips and to individual chips, thereby partitioning the module into testable partitions. These partitions permit testing of chip interconnections, chip functionality, and module functionality. Scan cell connections may be mask programmable so that the same multi-chip module base can be used for many different multi-chip module configurations.
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Tulloss and Yau, "Boundary Scan for Assembled Multichip Modules", AT&T Bell Laboratories, Engineering Research Center, publication date unknown.
Ellis & Bell, "Bottom-Up Techniques Propel Board Testability", Electronic Design, May 24, 1990, pp. 57-62.
Edwards Darvin R.
Heinen Katherine G.
Sparks Steve E.
Donaldson Richard L.
Hiller William E.
Honeycutt Gary C.
Jackson Jerome
Monin, Jr. Donald L.
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