Multi-bus multi-data transfer protocols controlled by a bus arbi

Details Multi-bus multi-data transfer protocols controlled by a bus arbi Multi-bus multi-data transfer protocols controlled by a bus arbi

1998-05-29

2000-08-15

Lee, Thomas C.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

710105, 710113, 710240, 710126, 714734, 714733, 714 45, 714736, 714738, 714 37, 371 224, 371 225, G06F 11277, G06F 1314, H04B 1700

Patent

active

061051543

ABSTRACT:
A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having multiple data lines for transferring data based on the data transfer protocols, a multiplexer coupled to the plurality of buses for multiplexing the data onto parallel lines and a CRC signature compactor coupled to the parallel lines for receiving the data. The CRC signature compactor compresses the data and (1) provides a fault-free signature representative of the data in a known fault-free chip, and (2) provides another signature representative of the data in a chip under test, wherein the two signatures are compared to determine whether a fault exists in the chip under test.

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Stephen B. Furber, VLSI RISC Architecture and Organization, Chapter 1, "The Evolution of Computer Architecture," M. Decker (1989) pp. 1-5.
Dhiraj K. Pradhan, "Fault-Tolerant Computing: Theory and Techniques," Prentice-Hall 1986, pp. 142-146.
Konemann et al., "Built-In Test for Complex Digital Integrated Circuits," IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980, pp. 315-319.

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