Multi-bit test circuit of semiconductor memory device

Details Multi-bit test circuit of semiconductor memory device Multi-bit test circuit of semiconductor memory device

1994-11-17

1996-01-09

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518902, 36518907, G11C 700

Patent

active

054834937

ABSTRACT:
The present invention relates to a semiconductor memory device and more particularly to a multi-bit test circuit which is capable of testing a data access operation of a plurality of memory cells at the same time. A multi-bit test circuit of a semiconductor memory device according to the present invention includes a multiplexer for outputting data having the same logic level to a plurality of data buses at the same time, a first comparator for determining as to whether the data inputted from the data buses has the same logic level, a test controller for complementarily activating the multiplexer and the first comparator with combining a test enable signal and read/write signals, a plurality of data input/output lines commonly connected to one of the data buses through a writing path and a reading path, a second comparator for receiving logic levels of the data input/output lines, and a data input/output controller for connecting one of the writing path and the reading path of the data input/output lines to the data buses in a first operation mode, and for transmitting an output of the second comparator to the data buses.

REFERENCES:
patent: 5315553 (1994-05-01), Morris
patent: 5321651 (1994-06-01), Monk
patent: 5359561 (1994-10-01), Sakomura et al.
patent: 5365481 (1994-11-01), Sawada

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