Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-05-12
2000-05-02
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365201, G11C 2900, G11C 700
Patent
active
060584955
ABSTRACT:
A multi-bit test circuit detects the fail cells in a memory block accurately even though there exists a short bridge between bit lines or between memory cells. The circuit includes an input buffer for transferring a same test data bit received from a multi-bit input/output pin to selected ones of the memory cells in each block in response to a multi-bit test enable signal, a plurality of sense amplifier drivers connected to the respective memory cells, for amplifying the test data bits to transfer the amplified data bits to the associated memory cells, and reading out the test data bits stored into the associated memory cells, and a comparator for comparing the same data bits stored into the same block to generate a comparison data bit in response to the multi-bit input/output enable signal, and transferring the comparison data to the multi-bit input/output pin.
REFERENCES:
patent: 4622653 (1986-11-01), McElroy
patent: 4744061 (1988-05-01), Takemae et al.
patent: 5075892 (1991-12-01), Choy
patent: 5228000 (1993-07-01), Yamagata
patent: 5587950 (1996-12-01), Sawada et al.
Lee Hi-Choon
Lee Jae-hyeong
Nguyen Hoa T.
Samsung Electronics Co,. Ltd.
LandOfFree
Multi-bit test circuit in semiconductor memory device and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-bit test circuit in semiconductor memory device and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-bit test circuit in semiconductor memory device and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1602685