Multi-bit test circuit and method thereof

Details Multi-bit test circuit and method thereof Multi-bit test circuit and method thereof

1996-12-16

1999-11-09

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714819, 365201, 365202, G11C 2900

Patent

active

059833750

ABSTRACT:
A multi-bit data block testing circuit and method thereof are described. The semiconductor memory device includes a multi-bit data block testing circuit for testing adjacent cell blocks using any one pattern selected from the same data pattern and a different data pattern during a multi-bit test mode. The multi-bit data block testing circuit further comprises a comparator operatively coupled to receive a data signal from each of the adjacent cell blocks. A multi-bit data block input source is interconnected with the multi-bit data block testing circuit via an input port and provides the data patterns during the multi-test mode. A multi-bit data block output receiver is interconnected with the multi-bit data block testing circuit via an output port and receives a test result indication from the comparator of the multi-bit data block testing circuit.

REFERENCES:
patent: 4692901 (1987-09-01), Kumanoya et al.
patent: 5305267 (1994-04-01), Haraguchi et al.
patent: 5313430 (1994-05-01), Rawlins et al.
patent: 5400281 (1995-03-01), Morigami
patent: 5483493 (1996-01-01), Shin
patent: 5673270 (1997-09-01), Tsujimoto

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