Multi-bit silicon nitride charge-trapping non-volatile...

Details Multi-bit silicon nitride charge-trapping non-volatile... Multi-bit silicon nitride charge-trapping non-volatile...

2005-05-24

2005-05-24

Tran, Michael (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S320000

Reexamination Certificate

active

06897533

ABSTRACT:
A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide
itride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.

REFERENCES:
patent: 5674768 (1997-10-01), Chang et al.
patent: 5929480 (1999-07-01), Hisamune
patent: 6147904 (2000-11-01), Liron
patent: 6512274 (2003-01-01), King et al.
patent: 6643170 (2003-11-01), Huang et al.

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