Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-11-29
2001-01-30
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S710000, C714S720000, C714S718000
Reexamination Certificate
active
06182262
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to memory devices having multi bank arrays.
BACKGROUND OF THE INVENTION
Integrated circuit memories such as dynamic random access memories have thousands of memory storage cells. These storage cells are typically fabricated as individual capacitors and arranged in rows and columns. The rows and columns of memory cells are referred to as a memory cell array. To insure that a memory device is fully operational, each of the individual memory cells is operationally tested. Further, the memory cells are tested in combination, or patterns, to identify possible failures due to coupling between adjacent memory cells or features.
As the population of memory cells in a memory device increase, the possibility of memory cell defects increase. Thus, more complex and time consuming tests are required for each memory device. In addition, some memory devices such as synchronous dynamic random access memories (SDRAMs) have multiple banks of memory cell arrays which must be tested.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an economical method of testing memory devices. In particular, an economical way of testing multiple bank memory devices is needed.
SUMMARY OF THE INVENTION
The above mentioned problems with memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A test method is described which allows multiple banks of memory arrays to be tested simultaneously.
In particular, the present invention describes a memory device comprising multiple banks of memory cells, a test mode trigger, control circuitry adapted to simultaneously perform a test on the multiple banks of memory cells in response to the test mode trigger, and error detection circuitry to receive test data and identify defective memory cells.
In another embodiment, a method of testing a memory device having multiple banks of memory cells is described. The method comprises the steps of initiating a test mode, simultaneously accessing the multiple banks of memory cells, storing data in the multiple banks of memory cells, and simultaneously reading data from the multiple banks of memory cells.
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Cady Albert De
Lamarre Guy
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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