Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-01-22
2001-10-09
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S230060
Reexamination Certificate
active
06301170
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a test circuit that shortens the time required to test semiconductor memory devices and a semiconductor memory device having the same.
2. Description of the Related Art
Since the beginning of their development, semiconductor memory devices have progressed significantly, with continual increases in performance and integration. As memory sizes increases, the time required to test the memories also increases. The increased test time delays the production cycle. Thus, efforts to shorten test times are ever on-going. Circuits have been designed and added to semiconductor devices to reduce test time. Meanwhile, in order to improve the input and output speed of semiconductor memory devices, semiconductor memory devices include a plurality of banks. A plurality of bits can be simultaneously inputted to/outputted from semiconductor memory devices including a plurality of banks.
Generally, when one-time row active and data input and output commands are applied in a normal operation mode of semiconductor memory devices, only one word line is selected in one bank corresponding to an address input from the outside. Information stored in a memory cell outputted onto a selected word line is amplified by a bit line sense amplifier and then outputted to the outside. For all word lines to be selected by a row active command, a one-time row active command must be applied at times which are equivalent to the number of banks multiplied by the number of word lines within a bank. All of the components involved in inputting/outputting data to/from a semiconductor memory device must be tested in order to ensure that the device functions properly. One can readily appreciates that as memory size becomes more dense, the time required for testing the increased memory locations and support circuits must also increase.
One way to shorten test time in a semiconductor memory device is the use of a refresh cycle reduction (RCR) mode. In the RCR mode, a plurality of banks are selected by a row active command. Therefore, a plurality of word lines are simultaneously activated by a one-time row active command, which allows a reduction in the test time. However, in this mode, since word lines within a plurality of banks are selected at the same time, more bit line sense amplifiers are operated at the same time, and more current is consumed accordingly. Since there is a limit to the amount of consumable current in a semiconductor memory device, the number of word lines which can be activated at the same time in a RCR mode is limited. Accordingly, a need exists for a device and method for conducting tests of a semiconductor memory device in a speeding fashion while minimizing current consumption.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor memory device that shortens testing time while minimizing the increase of current consumption.
The present invention further provides a test control circuit for controlling a predetermined test mode operation in such a way as to shorten the testing time in a semiconductor memory device.
The present invention further provides a test method of shortening the test time in a semiconductor memory device.
In one aspect of the present invention, there is provided a semiconductor memory device including at least one memory array including a plurality of word lines sharing a bit line sense amplifier. In the semiconductor device, at least two word lines among the plurality of word lines including the bit line sense amplifier are activated at the same time in a test mode.
In another aspect of the present invention, there is provided a test circuit in a semiconductor memory device including at least one memory array which has a plurality of word lines sharing a bit line sense amplifier. The test circuit according to a preferred embodiment of the invention includes a control signal generating circuit which generates a plurality of control signals at least one of which is activated in a test mode, and a row decoder which activates at least two word lines in response to the activated control signal and a predetermined row address signal comprised of a plurality of bits.
In yet anther aspect of the present invention, there is provided a test method in a semiconductor memory device including at least one memory array which has a plurality of word lines sharing a bit line sense amplifier. The test method according to a preferred embodiment of the invention includes the steps of: a) inputting a predetermined MRAD test signal through address pins; b) activating at least one control signal according to the predetermined MRAD test signal; and c) selecting at least two word lines at the same time according to the control signal and a predetermined row address signal.
The above test circuit and test method can shorten the testing time of a semiconductor memory device to be shortened without increasing current consumption.
REFERENCES:
patent: 5590080 (1996-12-01), Hasagawa et al.
patent: 5615166 (1997-03-01), Machida
F. Chau & Associates LLP
Le Vu A.
Samsung Electronics Co,. Ltd.
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